Semiconductor package and fabrication method thereof

Details Semiconductor package and fabrication method thereof Semiconductor package and fabrication method thereof

2005-01-11

2005-01-11

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Beam leads

C257S698000, C257S738000

Reexamination Certificate

active

06841872

ABSTRACT:
A semiconductor package and a fabrication method thereof can enhance adhesion between a solder and a package body by employing an irregular metal pattern, and improve stability. The semiconductor package includes a semiconductor substrate; a plurality of chip pads separately formed on an upper surface of the semiconductor substrate; an irregular metal pattern electrically connected to the plurality of chip pads; and an external terminal electrically connected to the metal pattern. In addition, a method of fabricating the semiconductor package includes the steps of separately forming a plurality of chip pads on an upper surface of a semiconductor substrate; forming an irregular metal pattern electrically connected to the plurality of chip pads; and forming an external terminal electrically connected to the metal of chip pads; and forming an external terminal electrically connected to the metal pattern.

REFERENCES:
patent: 6181569 (2001-01-01), Chakravorty
patent: 6235552 (2001-05-01), Kwon
patent: 6268642 (2001-07-01), Hsuan et al.
patent: 6278171 (2001-08-01), Arndt et al.
patent: 6291259 (2001-09-01), Chun
patent: 6291897 (2001-09-01), Wark et al.

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