Semiconductor package and fabrication method of the same

Details Semiconductor package and fabrication method of the same Semiconductor package and fabrication method of the same

2002-06-12

2003-09-30

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With dam or vent for encapsulant

C257S687000, C257S723000

Reexamination Certificate

active

06627979

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application claims the priority of Korean patent application Serial No. 2001-33946 filed on Jun. 15, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor package and, more particularly to a multi-type semiconductor package comprising a plurality of semiconductor chips and a fabrication method thereof.
2. Description of the Prior Arts
Recently, electronic apparatuses using semiconductor chips (semiconductor device), for example computer, PCS, cellular phone and PDA, have become of high performance, simpler to fabricate and smaller and more compact in the size. Accordingly, semiconductor chips and semiconductor packages applied to the electronic system also become smaller and more compact.
As is generally known, package methods of semiconductor chips include Multi Chip Module (MCM) package and Multi Chip Package (MCP).
The MCM package is a method that a plurality of semiconductor chips are adhered on a thin metal film, ceramic or substrate. Referring to
FIG. 4
, a plurality of semiconductor chips
402
,
404
and
406
are adhered on a base
400
such as a thin metal film, ceramic or substrate using wire bonding, tape bonding or flip chip bonding.
Referring to
FIG. 3
, the first semiconductor chip
402
is adhered by wire bonding, the second semiconductor chip
404
is adhered by tape bonding and the third semiconductor chip
406
is adhered by flip chip bonding, wherein a reference numeral
408
represents a PGA input/output terminal and
410
represents a BGA input/output terminal.
The MCP is a method that two or more semiconductor chips are mounted in a package of defined size, wherein a plurality of semiconductor chips are mounted on a lead frame or substrate using wire bonding. Referring to
FIG. 5
, a plurality of semiconductor chips
504
a
and
504
b
are loaded on a substrate
502
using wire bonding and pads of the semiconductor chips
504
a
and
504
b
are connected to an external lead
506
by a wire
508
, wherein the resulting structure is surrounded by epoxy molding compound (EMC)
500
.
However, the conventional MCM package and the MCP have limitations in realizing a small and compact size due to the structure that a plurality of semiconductor chips are adhered on a base such as a thin metal film, ceramic or substrate using wire bonding, tape bonding or a flip chip bonding, or that a plurality of semiconductor chips are mounted on a substrate using wire bonding and then, surrounded by epoxy molding compound.
And, the conventional package has a structure that a pad of semiconductor chip and the external lead are connected by wire, thereby there arises a problem of lowering the quality and reliability of semiconductor package (that is, degradation of electrical properties) and especially, the conventional package using EMC has a problem that reliability of semiconductor package is lowered drastically by alpha particle generated in the epoxy molding compound (EMC) and pollution in active region of device by EMC.
SUMMARY OF THE INVENTION
Therefore, the present invention has been proposed to solve the above problems and the primary objective of the present invention is to provide a semiconductor package capable of realizing a small and compact size and improving the reliability and the fabrication method of the same.
In order to accomplish the above objectives, the semiconductor package including a plurality of electrically-connected semiconductor chips according to the present invention comprises: a main semiconductor chip having a plurality of main chip pads and operating as a lead frame or a substrate; a plurality of metal patterns electrically connected to each corresponding main chip pad and having electrodes formed on both ends; one or more sub semiconductor chip adhered to the main semiconductor chip by adhering bumps formed on a plurality of sub chip pads to each corresponding electrode; a dam formed on the main semiconductor chip in a shape surrounding the inner electrodes except for the outer electrodes on the outmost region of the main semiconductor chip; filling materials filled up in the dam; and a plurality of solder balls adhered on the outmost electrodes.
In order to accomplish the above object, a method of fabricating semiconductor package including a plurality of electrically-connected semiconductor chips of the present invention comprises the steps of: a first process of forming a plurality of metal patterns connected to each corresponding main chip pad on the main semiconductor chip operating as a lead frame or a substrate and having electrodes formed on both ends thereof; a second process of forming a bump on each sub chip pad of sub semiconductor chip; a third process of adhering the sub semiconductor chip to the main semiconductor chip by adhering the bump to each corresponding electrode: a fourth process of forming a dam on the main semiconductor chip in a shape surrounding inner electrodes except for outer electrodes on the outmost region of the main semiconductor chip and then, filling up the inside thereof with filling materials; and a fifth process of adhering solder balls to the outmost electrodes.


REFERENCES:
patent: 5130275 (1992-07-01), Dion
patent: 5786230 (1998-07-01), Anderson et al.
patent: 6121682 (2000-09-01), Kim
patent: 6239367 (2001-05-01), Hsuan et al.
patent: 6291264 (2001-09-01), Tang et al.
patent: 6365432 (2002-04-01), Fukutomi et al.
patent: 6437990 (2002-08-01), Degani et al.

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