Semiconductor package and fabricating method thereof

Details Semiconductor package and fabricating method thereof Semiconductor package and fabricating method thereof

2003-07-25

2004-11-02

Thai, Luan (Department: 2827)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C438S106000, C438S111000, C438S112000

Reexamination Certificate

active

06812063

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor packages and fabricating methods thereof, and more particularly, to a semiconductor package which is compact in size and assured in quality, and a fabricating method thereof.
BACKGROUND OF THE INVENTION
A conventional QFN (Quad Flat Non-leaded) semiconductor package
10
, disclosed in U.S. Pat. No. 5,172,214 as illustrated in
FIG. 1
, includes a semiconductor chip
11
; a die pad
12
having a first surface
12
a
and a second surface
12
b
for attaching the chip
11
on the first surface
12
a
; a plurality of leads
13
disposed around the die pad
12
and electrically connected to the chip
11
; and an encapsulant
19
for encapsulating the chip
11
, the die pad
12
, and the leads
13
. The leads
13
each has a first portion
14
located closely to the chip
11
, a second portion
16
partially exposed to the outside of the encapsulant
19
, and an intermediate portion
15
for connecting the first portion
14
and the second portion
16
. The second portions
16
of the leads
13
serve as I/O terminals for electronic transmission so as to electrically connecting the semiconductor package
10
by means of solder balls (not shown) to a substrate such as an external printed circuit board (not shown). Furthermore, the electrical connection between chip
11
and the leads
13
can be achieved either through gold wires
17
as illustrated in left part of
FIG. 1
, or through solder balls
18
by means of a TAB (Tape Automated Bonding) technique as illustrated in right part of FIG.
1
. In addition, the die pad
12
has the second surface
12
b
thereof exposed to the outside of the encapsulant
19
, allowing heat generated by the chip
11
in operation to be dissipated to the outside of the semiconductor package
10
through the exposed surface
12
b
of the die pad
12
.
FIG. 2
illustrates another conventional QFN semiconductor package disclosed in U.S. Pat. No. 5,942,794. As shown in the drawing, this QFN semiconductor package
20
includes a semiconductor chip
21
; a die pad
22
for mounting the chip
21
thereon; a plurality of leads
23
electrically connected to the chip
21
through gold wires
27
; and an encapsulant
29
for encapsulating the chip
21
, the die pad
22
, the gold wires
27
and the leads
23
. The leads
23
each has a surface
23
a
partially exposed to the outside of the encapsulant
29
for serving as I/O terminals for electronic transmission so as to electrically connect the semiconductor package
20
to a substrate such as an external printed circuit board (not shown). The QFN semiconductor package
20
differs from the QFN semiconductor package
10
in
FIG. 1
in that the die pad
22
of the semiconductor package
20
with tie bars
25
thereof being bent upwardly is more elevated in position than the leads
23
, allowing the die pad
22
to be entirely encapsulated in the encapsulant
29
. Moreover, unlike the leads of the semiconductor package
10
in
FIG. 1
, the leads
23
in
FIG. 2
are not formed with a height difference therewithin.
Unlike conventional semiconductor packages such as QFP (Quad Flat Package) and SOP (Small Outline Package), the foregoing two QFN semiconductor packages are not provided with downwardly bent outer leads, which makes the QFN packages reduced in thickness to 0.85 mm, which is about half thick as a conventional package.
However, for fabricating the foregoing OFN packages, due to lack of adequate support or clamping force during molding the encapsulant, the die pad or the leads tend to be dislocated when a molding resin is injected rapidly, allowing a small amount of the molding resin to be squeezed into spacing between the die pad or the leads and a mold. As a result, flash occurs on the exposed surface
12
b
of the die pad or the exposed portion of the second portions
16
of the leads of the semiconductor package
10
in
FIG. 1
, or flash occurs on the exposed surfaces
23
a
of the leads of the semiconductor package
20
in
FIG. 2
, so that quality of the fabricated semiconductor package is severely degraded.
The foregoing flash problem can be solved by adhering a tape to a bottom surface of the die pad and leads for preventing flash from occurrence. However, during a wire-bonding process, a cushion effect provided by the tape may cause the leads to shift in position, which definitely degrade the wire-bonding quality.
Furthermore, the 0.85 mm OFN package may be out of date according to increased demand for even thinner electronic devices, and thus it is needed to further reduce the thickness of the QFN package.
In addition, the foregoing QFN packages have the leads thereof partially exposed to the outside of the encapsulant rather than entirely encapsulated in the encapsulant, which make contact area between the leads and the encapsulant reduced, allowing bonding strength to be deteriorated as well as delamination to be generated between the leads and the encapsulant, so that quality and liability of the QFN package are detrimentally affected.
SUMMARY OF THE INVENTION
A primary objective of the present invention is to provide a semiconductor package and a fabricating method thereof, which can effectively reduce the thickness of the semiconductor package and prevent delamination from occurrence.
In accordance with the foregoing and other objectives, the semiconductor package proposed in the invention comprises: a semiconductor chip having a first surface and a second surface; a plurality of leads disposed around the chip and having the same height as the semiconductor package, with strengthening structures being formed on sides of the leads; a plurality of connecting mechanisms formed at the leads and extending from surfaces of the leads toward the chip, for being electrically connected to the first surface of the chip and the leads; and an encapsulant for encapsulating the chip, the connecting mechanisms and the leads, with at least the second surface of the chip and upper and lower surfaces of the leads being exposed to the outside of the encapsulant.
The fabricating method of the foregoing semiconductor package of the invention comprises the following steps: providing a lead frame having a plurality of leads extending from a frame of the lead frame, wherein the leads are formed with strengthening structures on sides thereof, and a plurality of connecting mechanisms extend from surfaces of inner sides of the leads; attaching a supporting carrier to a bottom surface of the lead frame, mounting a semiconductor chip having a first surface and a second surface in a space on a surface of the carrier, wherein the space is predefined by the frame of the lead frame and the leads; electrically connecting the first surface of the, chip to the corresponding connecting mechanisms of the leads; performing a molding process to form an encapsulant in the space acting as a mold cavity defined by the frame of the lead frame and the leads; removing the carrier, and performing a singulating process to form individual semiconductor packages.
As concluded from the above mentioned, as compared with a conventional semiconductor package, the semiconductor package of the invention eliminates the use of a die pad, allowing the second surface of the chip to be exposed to the outside of the encapsulant, which simplifies the construction of the lead fame and makes the package further reduced to below 0.40 mm in thickness as well as improves the heat dissipating efficiency thereof.
Moreover, during the molding process, with the use of the space acting as the mold cavity predefined by the frame of the lead frame and the leads, the invention can adopt upper and lower molds with no mold cavity for forming the encapsulant, which allows the molding process to be performed for packages in various sizes, and saves the manufacturing cost for the molds. Furthermore, as the chip and the lead frame have bottom surfaces thereof attached to the supporting carrier, and the leads of the lead frame have the upper surfaces thereof tightly clamped by the upper mold, therefo

Affiliated with

Also associated with

Rating

Semiconductor package and fabricating method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor package and fabricating method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor package and fabricating method thereof will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3296023