Semiconductor package

Details Semiconductor package Semiconductor package

2001-08-31

2004-03-09

Smith, Matthew (Department: 2825)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

C257S666000, C257S672000, C257S673000

Reexamination Certificate

active

06703696

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor package in which a semiconductor device is mounted on a lead frame and the outside thereof, particularly the upper surface of the semiconductor device is encapsulated with molding compound.
2. Description of the Prior Art
In recent years, it has been necessary to miniaturize and shape semiconductor products mounted on a substrate so as to be thinner, since the packaging of the semiconductor is more dense. It has been required for LSI to reduce the number of chips by improving integration level and to miniaturize and make a package lighter. The popularization of so-called CSP (Chip Size Package) is rapidly increasing. Particularly, in the development of a thin semiconductor product with a lead frame, the semiconductor package of the single side encapsulation type has been developed in which a semiconductor device is mounted on a lead frame and the surface of semiconductor device mounted on a lead frame is encapsulated with molding compound.
FIG. 1
is a sectional view of one example of a semiconductor package.
FIG. 2
is a plan view thereof as seen through a molding compound. The semiconductor package shown in
FIGS. 1 and 2
is comprised of a lead frame
1
, a semiconductor device
4
mounted on a die-pad
3
supported with suspending leads
2
of lead frame
1
, metallic thin wires
6
for electrically connecting electrodes provided on the top face of the semiconductor device
4
with respective terminals
5
of lead frame
1
, and molding compound
7
for encapsulating the outside region of semiconductor device
4
including the upper side of semiconductor device
4
and the lower side of die-pad
3
. The semiconductor package is of the so-called non-lead type in which outer leads do not project from the semiconductor package and the two inner leads and outer leads are integrated into terminals
5
, wherein in the lead frame
1
, suspending leads
2
are directed upward in such a manner that die-pad
3
is positioned higher than terminals
5
. Since such a step is provided between die pads
3
and terminals
5
, molding compound
7
can be inserted into the lower side of die-pad
3
.
Since the semiconductor device is miniature, a matrix type frame is mainly used for the above-mentioned non-lead type of semiconductor package, in which plural semiconductor devices are arranged in a direction of a width of the matrix type frame. Further, recently, due to a demand for reduced cost, it is thought to switch over from a frame of the individually molded type shown in FIGS.
3
(A) and
3
(B) to a frame of the collectively molded type shown in FIGS.
4
(A) and
4
(B).
In the frame of the individually molded type, as shown in FIG.
3
(A), individual molding cavities C of a small size are provided separately within a frame F. After molding, individual semiconductor packages are stamped out so that semiconductor packages S shown in
FIG.
3
(B) are obtained. Namely, semiconductor devices are mounted on die-pads of lead frames through silver paste and others, and wire bonding is carried out. Thereafter, the respective semiconductor devices are individually molded with molding compound and the molded semiconductor devices are stamped out to form individual semiconductor packages.
In the frame of the collectively molded type, as shown in FIG.
4
(A), some molding cavities C of large size are provided within a frame F. Multiple semiconductor devices are arranged in a matrix within each molding cavity C, respectively and are collectively molded with molding compound. Thereafter, the collectively molded semiconductor devices are cut at grid-leads L by means of a dicing saw so that a semiconductor package S shown in FIG.
4
(B) is obtained. Namely, semiconductor devices are mounted on die-pads of lead frames through silver pastes and others and wire bonding is carried out. Thereafter, plural semiconductor devices are collectively molded with molding compound to a given cavity size, and then the collectively molded semiconductor devices are cut to form individual semiconductor packages by dicing.
In the above-mentioned non-lead semiconductor package, there is a type of semiconductor package in which a die-pad is exposed to increase the effect of heat radiation, and bonding of some electrodes of the semiconductor device to the surface of the die-pad
3
is needed for grounding.
FIG. 5
is a sectional view of such a type of semiconductor package.
FIG. 6
is a plan view of the semiconductor package seen through the molding compound thereof. When producing the collectively molded semiconductor packages, each semiconductor device
4
is mounted on the die-pad
3
of lead frame
1
through silver paste and others. Thereafter, given electrodes on the top face of each semiconductor device
4
are connected with terminals through wires
6
, and the other electrodes on each semiconductor device
4
are connected with the surface of die-pad
3
through wire
8
. Thereafter, semiconductor devices are collectively molded with molding compound
7
, and then as above-mentioned, the collectively molded semiconductor devices are cut to form individual semiconductor packages. In this case, in a type of semiconductor package shown in
FIG. 1
, silver plating (not shown) is made on the wire connecting points of terminals
5
in lead frame
1
, while in a type of semiconductor package shown in
FIG. 5
, silver plating is made also on the surface of die-pad
3
.
When mounting the semiconductor package shown in
FIG. 5
on a printed circuit board, solder plating is made not only on the exposed portions of terminals
5
, but also on the exposed portions of die-pad
3
. Further, solder cream is applied on the areas on a printed circuit board corresponding to the exposed portions of terminals
5
and die-pad
3
. The semiconductor package mounted on a printed circuit board is heated in an oven at about 230° C., by which solder is made to re-flow so that the semiconductor package is fixed firmly at a given position on a printed circuit board.
However, in the semiconductor package shown in
FIG. 5
, stress is applied to the contact point of die-pad
3
to wires
8
when making solder re-flow from a difference in thermal expansion coefficient between the molding compound
7
and the copper material of lead frame
1
, and the adhesion of portions of plated silver for connecting of wires applied on the surface of die-pad to molding compound
7
is not enough so that the trouble of coming-off of wires occurs. Further, there is a case where a crack is generated in the molding compound from the neighborhood of the corners of the die-pad as the starting point, wherein there is the possibility of cutting of wires occurs according to a state of crack.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor package in which bonding of some electrodes of the semiconductor device to the surface of a die-pad for grounding is made, wherein no trouble of coming-off of wires or cutting of wires occurs.
In order to achieve the above-mentioned object, a semiconductor package of the present invention comprises a semiconductor device mounted on a die-pad supported by suspending leads of a lead frame, wires for electrically connecting given electrodes arranged on a top face of the semiconductor device with terminals of the lead frame, wires for bonding the other electrodes arranged on the top face of the semiconductor device to the surface of the die-pad for grounding and a molding compound for encapsulating an outer area of the semiconductor device including all the wires, while the lower face of the die-pad and the lower face and side face of the terminals are exposed, wherein portion(s) plated with silver for connecting of the wires on the surface of the die-pad are formed at points positioned between a peripheral edge of the die-pad and an outer edge of the semiconductor device while leaving spaces from both the edges.


REFERENCES:
patent: 5032895 (1991-07-01), Horiuchi et al.
patent: 5153706 (1992

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