Semiconductor package

Details Semiconductor package Semiconductor package

2001-09-06

2003-08-05

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

With shielding

C257S660000, C257S697000, C257S710000, C257S724000, C257S728000

Reexamination Certificate

active

06603193

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor packages. More particularly, the present invention relates to semiconductor packages having a cavity.
2. Background of the Invention
Modern electronic devices, for example cellular phones and pagers, require a seamless integration of analog and digital subsystems. Furthermore, premiums are often placed on small size, complexity, and high performance. Thus, highly sensitive analog circuits frequently need to be placed very close to high-speed digital systems.
High-speed digital systems can switch more then one hundred million times a second. At such switching speeds, switching currents tend to be high. Thus, such high-speed digital systems can radiate energy that interferes with highly sensitive analog circuits. Interference usually takes the form of signal crosstalk. While faraday shielding has been widely used to protect highly sensitive analog circuits from interference, the traditional faraday shields tend to be expensive. Furthermore, their implementation must be undertaken with great foresight to determine where to install the shields, and with great care to actually protect the analog circuits. Moreover, the traditional faraday shield is not particularly flexible.
Traditionally, an integrated circuit is supplied as part of a semiconductor package having external leads for soldering, or otherwise connecting, to a printed circuit board. For example, dual in-line packages (DIP) and surface mount leadless packages have been widely used with integrated circuit chips. In such packages, an integrated circuit chip is encapsulated in a ceramic or plastic housing having electrical leads that are suitable for soldering to a circuit board. Bonding conductors, which are also encapsulated in the housing, extend from the upper part of the electrical leads, which are within the package, to electrical pads on the integrated circuit chip. Typically, the bond conductors are welded to the external electrical connectors and to the electrical pads.
A typical prior art semiconductor package is illustrated in
FIGS. 1A-1D
. Referring now to
FIG. 1A
, that prior art package includes a lead frame
200
, which is usually stamped out of a metal strip. The lead frame includes a plurality of leads
202
held together by connectors
204
that extend between rails
206
. The lead frame further includes a mounting pad
208
. Referring now to
FIG. 1B
, which shows a cut-away view along line A—A of
FIG. 1A
after an integrated circuit chip
210
is mounted on the mounting pad
208
, bonding conductors
212
extend from exposed electrical connectors
214
on the integrated circuit chip
210
to the leads
202
. Typically the bonding conductors
212
are welded to the exposed electrical connectors and to the electrical pads. Next, as shown in
FIG. 1C
, the lead frame
200
, the integrated circuit chip
210
, and the bonding conductors
212
are then encapsulated. Finally, as shown in
FIG. 1D
, the leads
202
are then cut and formed as required to complete the semiconductor package
220
. While not specifically discussed, the rails
206
and the connectors
204
are separated from the pad
208
and the leads
202
at some time during assembly. The leads
202
enable electrical signals to travel to and from the integrated circuit chip to the external environment.
Because the dual in-line package is a relatively large structure that prevents high-density packaging, surface mount leadless packages have become popular. However, denser packaging increases the cross-talk problem. Furthermore, many analog circuits have a high impedance level that makes them particularly sensitive to crosstalk. So, while useful, most surface mount leadless packages provide inadequate electrical and electromagnetic isolation of their components.
Another type of semiconductor package, one that is a hybrid of the surface mount leadless package and the “pin” type package, is possible. Such a semiconductor package has “pins” that extend from the bottom of the package. Those pins are designed to attach to pads on the surface of a printed circuit board. As electrical connections are not made along the edges of the package, adjacent semiconductor packages can abut, which allows dense packaging. While beneficial, this also increases the cross-talk problem.
Therefore, a semiconductor package that provides electrical and electromagnetic isolation of a component mounted therein would be beneficial. More beneficial would be a semiconductor package that enables dense packaging of semiconductor components, together with electrical and electromagnetic isolation. Even more beneficial would be a low cost semiconductor package that enables dense packaging of integrated circuit chips, together with electrical and electromagnetic isolation of those chips.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a semiconductor package that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
The features and advantages of the invention will be set forth in the description that follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
The principles of the present invention provide for a semiconductor package that enables packaging of integrated circuit chips (or other semiconductor components), together with electrical and electromagnetic isolation, and that can be made available at low cost. A semiconductor package according to the principles of the present invention comprises a molded body that retains a plurality of contact pins, and that beneficially also retains an RF shield. The lower portion of the contact pins extend from the bottom of the molded body, while the upper portions of the contact pins are exposed in an interior chamber of the molded body. The RF shield is beneficially molded into the body and forms a protected cavity suitable for holding a first integrated circuit. Beneficially, bonding conductors electrically connect pads on the first integrated circuit to the tops of the contact pins. This enables electrical signals to be supplied to and from the first integrated circuit. The RF shield can be electrically grounded via a bonding conductor.
The molded body beneficially also includes an unprotected cavity for holding a second integrated circuit. The unprotected cavity beneficially includes a beveled wall nearest the protected cavity. Bonding conductors can then interconnect the first integrated circuit, the second integrated circuit, and the tops of the contact pins, as required, to enable electrical signals to flow. The bonding conductors that interconnect the first integrated circuit and the second integrated circuit are beneficially located such that they pass at a shallow angle over the beveled wall.
The molded body has top surfaces for receiving a cover, beneficially comprised of copper. Beneficially, the top surfaces are formed on an interior wall set that is separated from an exterior wall set by a channel. A sealing compound is placed in the channel, and the cover is placed on the top surfaces, thus forming a finished semiconductor package.
Beneficially, the pins are pushed into openings formed in the molded body. A sealing compound in then located over the pins to environmentally seal the semiconductor package.


REFERENCES:
patent: 5151769 (1992-09-01), Immorlica et al.
patent: 5194695 (1993-03-01), Maslakow
patent: 5248901 (1993-09-01), Temple
patent: 5285107 (1994-02-01), Kazami et al.
patent: 5350713 (1994-09-01), Liang
patent: 5572065 (1996-11-01), Burns
patent: 5574314 (1996-11-01), Okada et al.
patent: 5650659 (1997-07-01), Mostafazadeh et al.
patent: 6227724 (2001-05-01), Verdiell
patent: 6365960 (2002-04-01), Pollock et al.
Patent application Ser. No. 09/946,553, filed Sep. 6, 2001, Crane,

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