Semiconductor package

Details Semiconductor package Semiconductor package

2001-10-17

2003-04-29

Whitehead, Jr., Carl (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Ball or nail head type contact, lead, or bond

C257S783000

Reexamination Certificate

active

06555921

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor packages and methods for manufacturing the semiconductor packages, and more particularly to chip scale packages and a method for manufacturing the chip scale packages at the wafer level, using a rerouting film and solder connection.
2. Description of the Related Arts
The electronics industry has been progressing with the miniaturization of electronic devices. This trend influences semiconductor packaging technology, which enables the connection between bare IC chips and other components. Typically, a semiconductor package has a footprint much larger than that of the chip. To adapt to the miniaturization trend, the size difference between the package and the chip has been reduced, producing a new package type called a Chip Scale Package (or a Chip Size Package) (CSP). Among the manufacturing technologies for the CSPs is Wafer Level Chip Scale Packaging, which assembles CSPs at the wafer level, rather than separately processing individual chips.
FIG. 1
schematically shows a semiconductor wafer
10
, which includes integrated circuit chips
20
and scribe lines
14
dividing the chips
20
. As shown in
FIG. 2
which is an enlarged view of part ‘A’ of
FIG. 1
, chip pads
22
are on each chip
20
, and a passivation layer
24
covers the upper surface of the IC chip
20
except where openings through the passivation layer
24
expose the chip pads
22
.
Regarding to
FIGS. 3 and 4
, in conventional wafer level chip scale packaging, a dielectric layer
36
and solder bumps
38
are formed on the surface of the wafer
10
. The solder bumps
38
electrically connect to the chip pads
22
of FIG.
2
. Then, a sawing apparatus separates the wafer
10
along the scribe lines
14
, producing individual CSPs
30
.
FIG. 4
illustrates the cross-sectional structure of the CSP
30
. The solder bump
38
connects to the chip pad
22
through a metal layer
34
, and a first and a second dielectric layers
32
and
36
are respectively on and under the metal layer
34
. Integrated circuits (not shown) are under the chip pad
22
and the passivation layer
24
. In the fabrication of the CSPs
30
on the wafer
10
, the first dielectric layer
32
is formed and patterned on the wafer
10
such that openings in the first dielectric layer
32
expose the chip pads
22
. Then, the metal layer
34
is formed on the first dielectric layer by metal deposition and patterning, so that the metal layer
34
contacts the chip pads
22
. The second dielectric layer
36
is formed on the metal layer
34
such that openings in the second dielectric layer
36
expose a portion of the metal layer
34
. Finally, solder bumps
38
are formed on the exposed portion of the metal layer
34
. As described above, sawing separates individual CSPs
30
.
The CSPs manufactured by the above-described manufacturing method have several problems. First, coating and high-temperature curing of the dielectric layers may apply thermal stress to the integrated circuits below the dielectric layers, damaging the integrated circuits. The thinner the dielectric layers are, the smaller the thermal stress is. However, making the dielectric layer thin increases the capacitance of the CSP. Second, when the CSP is mounted on an external circuit board such that the solder bumps contact the circuit board, the connection integrity between the solder bumps and the circuit board is not reliable. Third, since defective chips as well as good chips are packaged in wafer level, the manufacturing cost of individual CSPs increases.
SUMMARY OF THE INVENTION
The present invention is directed to chip scale packages and methods for manufacturing the chip scale packages. The methods fabricate multiple chip scale packages of integrated circuits simultaneously, and separate the chip scale packages by sawing. The individual chip scale packages can be mounted on a circuit board of an electronic device.
One manufacturing method includes: providing a rerouting film having a metal pattern layer, terminal pads on the metal pattern layer, and via holes exposing portions of the metal pattern layer; attaching a semiconductor wafer having integrated circuits and chip pads to the rerouting film, such that the chip pads correspond to the via holes, and a polymer layer is between the wafer and the rerouting film, filling the via holes; removing the polymer layer to the extent that the chip pads and the metal pattern layer in the via holes are exposed; filling in each of the via holes with solder, to electrically connect the chip pads to the metal pattern layer; forming external terminals on the respective terminal pads of the rerouting film; and separating the wafer and the rerouting film into individual packages, each package including an integrated circuit having a corresponding portion of the rerouting film attached thereon. The method further includes forming a protection layer on the solder filling.
Another method for manufacturing semiconductor packages is basically the same as the method described above. A difference is that instead of the semiconductor wafer, individual integrated circuit chips are attached to the rerouting film.
In accordance with an embodiment of the present invention, a semiconductor package includes: a semiconductor integrated circuit having chip pads; a substrate attached to the semiconductor integrated circuit so that via holes of the substrate are above the chip pads; solder fillings in the via holes, the solder fillings electrically connecting the chips pads to the pattern metal layer; and another dielectric layer between the substrate and the semiconductor integrated circuit. The substrate includes: a patterned metal layer; terminal pads formed on the patterned metal layer; a dielectric layer overlying the patterned metal layer, the dielectric layer having openings to expose the patterned metal layer; and the via holes. The semiconductor package further includes: external terminals connecting to the terminal pads; interconnection bumps, which are formed on the respective chip pads; and polymer protection layers on the solder fillings.


REFERENCES:
patent: 5895229 (1999-04-01), Carney et al.
patent: 6071755 (2000-06-01), Baba et al.
patent: 6097087 (2000-08-01), Farnworth et al.
patent: 6232666 (2001-05-01), Corisis et al.
patent: 6351030 (2002-02-01), Havens et al.
patent: 6376279 (2002-04-01), Kwon et al.
patent: 6414849 (2002-07-01), Chiu

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