Semiconductor package

Details Semiconductor package Semiconductor package

2001-06-05

2002-10-22

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

C257S666000, C257S668000, C257S672000, C257S676000, C257S787000

Reexamination Certificate

active

06469399

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor package, and more particularly to a package encapsulant formed by means of filling molten liquid plastic material simultaneously into upper and lower molds to thereby packaging an electric element or chip on a substrate panel.
DESCRIPTION OF THE RELATED ART
As ICs (integrated circuits) include a larger number of circuits, use larger silicon areas, and operate at increasingly higher clock frequencies, surface-mounted packages for ICs are correspondingly required to have increasingly higher lead counts, smaller footprints and higher electrical and thermal performance, while at the same time achieving at least existing accepted reliability standards. Conventional lead frame based packages can deliver satisfactory thermal and electrical performance up to about 300 leads.
U.S. Pat. No. 5,313,102A discloses a typical lead frame based package in which a semiconductor circuit (chip) is positioned on a mount support pad lying on a lead frame. Wirebonds are connected near the outer edges of the semiconductor chip, bonding the chip to lead fingers of the lead frame. An encapsulating material surrounds the chip, parts of the lead fingers of the lead frame, wirebonds, so that the IC package device can be surface mounted to a printed circuit board (PCB). The resulting package has a size significantly larger than that of the semiconductor chip.
For semiconductor packages having the lead count above 300 leads, other technologies, such as BGA (ball grid array), are developed. BGA is a leadless package on which the connectors to the board have been placed in an array on the bottom of the package. They are attached to the board with tiny balls of solder placed on each contact. Available in plastic and ceramic varieties, BGA is noted for its compact size, high lead count and low inductance, which allows lower voltages to be used. BGA chips are easier to align to the printed circuit board, because the balls are farther apart than leaded packages. Since the balls are underneath the chip, BGA has led the way to chip scale packaging (CSP) where the package is not more than 1.2 times the size of the semiconductor die itself.
A conventional chip package which is suitable for use in BGA applications is illustrated in FIG.
1
. In the conventional chip package, a die pad
12
is provided below a hole
11
in the substrate panel
10
for mounting a chip
20
to the substrate panel
10
. The substrate panel
10
is usually a flat board which extends continuously substantially throughout its entire area without interruption except for the hole
11
in a central region of the substrate panel
10
. Typically, the substrate panel
10
is a PCB with a plurality of leads (not shown) formed thereon or therein. The leads of the substrate panel
10
are connected with corresponding bonding pads (not shown) formed on the chip
20
by wires
21
.
Molten liquid plastic material is filled into a mold (not shown) and becomes a package encapsulant
22
after it has been hardened so as to package an underside of the chip
20
and the die pad
12
which are exposed on the underside of the substrate panel
10
. The mold is removed after the encapsulant
22
has been hardened. Wires
21
on the upper side of the chip
20
cannot be packaged by the mold at the same time as the substrate panel
10
forms an obstacle. It is noted that this problem does not occur in a lead frame based semiconductor package since the molten liquid plastic material can pass, between the lead fingers, from the underside to the upper side of the lead frame.
A solution to package the wires
21
that extends beyond the hole
11
to the upper side of the substrate panel
10
is to drop molten liquid plastic material onto the substrate panel
10
in the area surrounding the wires
21
to form a package encapsulant
23
. The encapsulant
23
covers an upper side of the chip
20
that is exposed on the upper side of the substrate panel
10
, thereby providing a completely air tight seal for the chip
20
. It is, however, found that the package encapsulant
23
has an irregular shape and a rugged surface, and the wires
21
are exposed, as the spread of the molten liquid plastic material dropped on the substrate panel
10
cannot be controlled. In addition, the dropping of the molten liquid plastic material must be proceeded in a vacuum environment to avoid generation of air bubbles in the encapsulant
23
which may cause so-called vapor explosion.
SUMMARY OF THE INVENTION
It is a primary object of the present invention to provide a semiconductor package, in which the package encapsulant is formed on both the upper side and the underside of the chip by using molds to control the amount of material needed for forming the package encapsulant, and to avoid exposure of the wires and generation of air bubbles.
In accordance with the present invention, a substrate panel with a central hole is provided, and a die pad is mounted to the underside of the substrate panel around the hole. A chip is then mounted to a underside of the die pad, and a plurality of wires interconnect leads on the chip with leads on the upper side of the substrate panel. An upper mold is placed on the upper side of the substrate panel above the hole, and a lower mold is placed on the underside of the substrate panel below the hole. Each of the upper mold and the lower mold includes a mold gate through which molten liquid plastic material is poured into the molds so as to form an upper package encapsulant and a lower package encapsulant on the upper side and the lower side of the substrate panel, respectively, thereby providing a completely air tight environment for the chip.
Since the molten liquid plastic material is poured onto the upper and lower sides of the substrate panel by using molds, the problems of irregular shape of the package encapsulant, rugged surface of the package encapsulant, exposure of wires, and generation of air bubbles in the package encapsulant in the conventional technique can all be prevented.
Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5313102 (1994-05-01), Lim et al.
patent: 5637916 (1997-06-01), Joshi
patent: 5898212 (1999-04-01), Kim
patent: 6036173 (2000-03-01), Neu et al.

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