Semiconductor package

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead

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Details

257787, 257690, 257693, 257691, G01L 2348

Patent

active

058616683

ABSTRACT:
A semiconductor package of the present invention includes a paddle layer having a metal wiring pattern formed therein, semiconductor chips bonded on at least one surface of the paddle layer. A plurality of wires electrically connecting a plurality of chip pads formed on the semiconductor chips with the paddle layer. Each lead includes a first lead bonded to a surface of the paddle layer and a second lead which is at least partially exposed. A conductive adhesive bonds the paddle layer to the first leads and a molding resin comprises the body of the package. The semiconductor package of the above construction has various advantages compared to conventional packages. The occupying area rate can be minimized, and an undesired curving of the lead can be prevented. Further, since the semiconductor chip can be bonded on both surfaces of the paddle layer, an integrated semiconductor package can be achieved.

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patent: 5444301 (1995-08-01), Song et al.
patent: 5471088 (1995-11-01), Song
patent: 5483024 (1996-01-01), Russell et al.
patent: 5648680 (1997-07-01), Ogawa et al.
patent: 5677566 (1997-10-01), King et al.

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