Semiconductor package

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package

Reexamination Certificate

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Details

C257S416000, C257S680000, C257SE33058, C257SE23104, C257SE21299

Reexamination Certificate

active

08053877

ABSTRACT:
A semiconductor package includes a chip base material; a capacitor formed on the base material; and a cover formed over the base material to cover the capacitor, and having a side portion and an upper portion. The base material is provided with a bonding pattern connecting the base material and the cover to cover the capacitor. The bonding pattern includes a region A having a substantially uniform pattern width A, and at least one region B having a pattern width B which is larger than the width pattern width A.

REFERENCES:
patent: 6043556 (2000-03-01), Tomie
patent: 6303986 (2001-10-01), Shook
patent: 6376907 (2002-04-01), Takano et al.
patent: 2008/0211073 (2008-09-01), Hatakeyama
patent: 2000-231945 (2000-08-01), None
patent: 2001-257456 (2001-09-01), None
patent: 2005-167507 (2005-06-01), None
patent: 2007-201356 (2007-08-01), None

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