Semiconductor package

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Solder wettable contact – lead – or bond

Reexamination Certificate

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Details

C257SE23023, C257S773000, C257S780000, C257S786000

Reexamination Certificate

active

07830022

ABSTRACT:
A semiconductor package is disclosed. One embodiment provides a semiconductor package singulated from a wafer includes a chip defining an active surface, a back side opposite the active surface, and peripheral sides extending between the active surface and the back side; a contact pad disposed on the active surface; and a metallization layer extending from the contact pad onto a portion of the peripheral sides of the chip.

REFERENCES:
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patent: 5639013 (1997-06-01), Jairazbhoy et al.
patent: 5656547 (1997-08-01), Richards et al.
patent: 5684677 (1997-11-01), Uchida et al.
patent: 5818107 (1998-10-01), Pierson et al.
patent: 5936846 (1999-08-01), Jairazbhoy et al.
patent: 6285085 (2001-09-01), Taguchi
patent: 6597059 (2003-07-01), McCann et al.
patent: 7019397 (2006-03-01), Ohuchi et al.
patent: 2006/0118938 (2006-06-01), Tandy
Edward Furgut, “Taking Wafer Level Packaging to the Next Stage: A 200 mm Silicon Technology Compatible Embedded Device Technology”, SEMICON Europa 2006, Munich, Germany (17 pgs).
M. Brunnbauer, “An Embedded Device Technology Based on a Molded Reconfigured Wafer”, 2006 ECTC San Diego, May 31-Jun. 1, 2006 (5 pgs.).

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