Semiconductor P-I-N detector

Details Semiconductor P-I-N detector Semiconductor P-I-N detector

1997-10-10

2001-07-03

Mintel, William (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Electromagnetic or particle radiation

C257S441000, C257S442000, C257S458000, C250S370090, C250S370120, C250S370130, C250S370140

Reexamination Certificate

active

06255708

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the detection of high energy radiation, such as gamma rays and x-rays, by a semiconductor detector and also concerns the methods for fabricating the semiconductor radiation detector. More particularly, the invention concerns semiconductor detectors having a P-type layer/Intrinsic layer/N-type layer (hereinafter “P-I-N”) structure.
BACKGROUND OF THE INVENTION
High energy semiconductor radiation detectors provide detection of gamma rays and x-rays in numerous fields including nuclear instrumentation, medical imaging, biological research, astronomy, and dosimetry. However, known high energy scintillator-based detectors fail to provide acceptable energy resolution while operating at room temperature. For instance, the known high energy detectors are ill-suited for use in gamma ray spectrometers operating at room temperature.
Currently available Metal-Semiconductor-Metal (hereinafter “MSM”) devices have proven useful for several spectroscopic applications. MSM detectors tend to have reasonably good energy resolution, typically 5% at 120 keV at room temperature. However, MSM detectors suffer from particular drawbacks. For instance, MSM detectors lack the energy resolution necessary to meet the requirements for spectroscopic applications. Additionally, the known MSM detectors are severely limited by their high inter pixel leakage current.
Others have attempted to overcome the drawbacks associated with MSM detectors by either increasing the bias voltage applied across the detectors or by cooling the detectors to a temperature less than −30° C. Increasing the bias voltage across the MSM detectors, however, increases the leakage current through the detectors. The increased leakage current degrades the energy resolution of the detector. Additionally, cooling the MSM detectors, especially large arrays of detectors, proves to be problematic because of the quantities of power consumed to cool the detectors. An alternative to the MSM detector is the P-I-N detector.
The P-I-N design can offer low leakage current at large bias voltages, relative to MSM detectors. A basic P-I-N semiconductor radiation detector includes a wafer of intrinsic material with doped contacts formed on the opposite surfaces of the intrinsic layer. A reverse biasing electric field is applied across the contacts. High energy radiation, such as gamma rays, passing through the wafer of intrinsic material liberate electron-hole pairs which are swept to the respective contacts by the electric field and generate electrical pulses in an associated electronic unit.
Rhiger, U.S. Pat. No. 5,391,882, discloses a P-I-N type gamma ray detector having an intrinsic layer formed of cadmium telluride (CdTe) or cadmium zinc telluride (CdZnTe). The P-type and N-type semiconductor layers are formed of mercury cadmium telluride (HgCdTe). The intrinsic layer is a wide bandgap semiconductor detector layer, and the doped layers are graded such that the bandgap of the doped layers decreases with distance from the intrinsic layer.
The P-I-N detector disclosed in the Rhiger Patent is manufactured by growing a CdZnTe substrate and then forming HgCdTe layers by liquid phase epitaxially growth techniques. Even though this approach produces gamma ray detectors having higher energy resolution than MSM detectors, the fabrication method is expensive and is not useful for High Pressure Bridgman (HPB) CdZnTe because of the high temperatures used during the liquid phase epitaxially growth phase. Several researchers have observed that high temperatures (greater than 150 degrees C or perhaps lower, depending on the anneal time) severely degrade the resistivity and detector properties of HPB CdZnTe. Since liquid phase epitaxy growth of HgCdTe layers is typically done around 400 to 550 degrees C, this process is not suitable for HPB CdZnTe.
Another method known in the art for forming P-I-N detectors relies on thermal diffusion. On one side of the CdZnTe substrate, indium is thermally diff-used to form an N
+
layer, and on the other side a thin Au layer is deposited to provide a P
+
contact. The drawback of this approach is that indium, in addition to being a donor, forms defect complexes which could degrade the energy resolution. Also, detectors fabricated by this process exhibit poor stability.
Accordingly, it is an object of the invention to provide a semiconductor P-I-N detector that has low leakage current and that can operate at room temperature. These and other objects will be apparent from the description that follows.
SUMMARY OF THE INVENTION
Generally speaking, in the present invention a semiconductor P-I-N detector includes a boundary layer for reducing the leakage current within the P-I-N detector. The boundary layer is positioned between a doped layer in the detector and an intrinsic wafer that generates an electrical current as a function of impacting high energy radiation. The boundary layer acts to reduce the diffusion of dopant from the doped layer into the intrinsic wafer. By reducing the diffusion of dopant, the boundary layer also reduces the leakage current within the P-I-N detector.
A multilayer semiconductor P-I-N device for detecting high energy rays, according to the invention, includes an intrinsic wafer, a doped layer overlying the top surface of the intrinsic wafer, an oppositely doped layer overlying the bottom surface of the intrinsic wafer, and a boundary layer. The boundary layer is oriented between one of the doped layer and the intrinsic wafer, such that the boundary layer reduces the diffusion of dopant into the intrinsic wafer. The intrinsic wafer generates an electrical current in response to impacting high energy rays, while the boundary layer reduces the leakage current through the P-I-N detector. The resulting P-I-N detector exhibits good diode behavior with a very low leakage current at room temperature.
The intrinsic wafer is described as having a top surface and a bottom surface, however, the terms “top” and “bottom” are arbitrary terms used simply to assist in describing the structure of the P-I-N detector. The intrinsic wafer can be flipped so that the bottom surface becomes the top surface, and vice versa, without impairing the operation of the P-I-N detector.
In one aspect of the invention, the intrinsic wafer can be formed of CdZnTe crystals or CdTe. Further in accordance with the invention, the doped layers can be formed of compounds selected from groups II and VI of the periodic table of the elements. Preferably, the semiconductor P-I-N detector includes an N-doped layer formed of cadmium sulfide doped with indium, and a P-doped layer formed of zinc telluride doped with copper.
Other aspects of the invention provide for at least one boundary layer formed of compounds selected from groups II and VI of the periodic table of the elements. The boundary layers are preferably formed of II-VI compounds that match the II-VI compounds found in the adjacent doped layer.
Further features of the invention include deposited semiconductor layers within the P-I-N detector. In particular, the material forming the boundary layers and/or the doped layers can be formed of deposited materials. The deposited semiconductor layers form a remarkably accurate P-I-N detector that does not suffer from the performance degradation caused by the high temperature manufacturing methods typically employed in the past.
The process for the fabrication of this P-I-N device includes the steps of providing an intrinsic wafer, forming a semiconductor boundary layer that overlies the top surface of the intrinsic wafer, forming a doped layer overlying the boundary layer, and forming an oppositely doped layer that overlies the bottom surface of the intrinsic wafer.
Another aspect of the invention provides for forming the boundary layer by depositing a layer of semiconductor material onto the intrinsic wafer. Further in accordance with this aspect of the invention, the doped layer adjacent the boundary layer can be formed by doping the surface of the boundary layer with a dopant.

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