Semiconductor output circuit

Details Semiconductor output circuit Semiconductor output circuit

2000-04-14

2002-05-14

Smith, Matthew (Department: 2825)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S317000

Reexamination Certificate

active

06388496

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-107632, filed Apr. 15, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor output circuit that can protect such a circuit as reverses the potentials of a collector and an emitter of a bipolar transistor.
A problem of an output circuit for driving an inductive load is that it is often damaged by a counter electromotive force from the inductive load.
FIG. 1
shows an example of a conventional output circuit. This output circuit
1
is comprised of a driving circuit
2
, and a push-pull circuit consisting of a PNP transistor Q
1
and an NPN transistor Q
2
. An output Vout of the output circuit
1
is connected to one of the terminals of an inductive load
3
. As means for preventing an output section from being broken down by a counter electromotive force from the inductive load
3
, a technique is known which connects protective diodes D
1
, D
2
in parallel to the transistors Q
1
, Q
2
.
In the conventional output circuit, the diodes D
1
, D
2
are added outside the semiconductor chip on which the output circuit is formed. Therefore, the total device size becomes very large. An object of the present invention is to integrate these protective diodes D
1
, D
2
on the semiconductor chip to reduce the total device size.
Such a technique as shown in
FIG. 1
allows the diodes D
1
, D
2
to absorb currents I
ZH
, I
ZL
generated by a counter electromotive force from the inductive load
3
to preclude a voltage at the output terminal Vout of the power output circuit
1
from exceeding withstand voltages of the transistors Q
1
, Q
2
, thereby preventing breakdown of the transistors Q
1
, Q
2
.
The withstand voltages of the bipolar transistors Q
1
, Q
2
constituting the push-pull circuit include collector-emitter withstand voltages Vceo
1
, Vceo
2
for a forward operations of the Q
1
, Q
2
and emitter-collector withstand voltages Veco
1
, Veco
2
for reverse operations involving the reversal of voltages at the collector and emitter of the transistor.
As described above, when a counter electromotive force from the inductive load
3
increases the output terminal voltage Vout of the output circuit
1
beyond a power source voltage Vcc, the voltages at the collector and emitter of the PNP transistor Q
1
are reversed. Then, when the potential difference exceeds Veco
1
, the transistor Q
1
is broken down. In addition, if the output terminal voltage Vout of the output circuit
1
decreases below the ground, the voltages at the collector and emitter of the transistor Q
2
are reversed. Then, if the potential difference exceeds Veco
2
, the transistor Q
2
is broken down.
To sufficiently increase the values of the withstand voltages Veco
1
, Veco
2
for reverse operations, impurities in base and emitter regions of the transistors Q
1
, Q
2
must be diffused deeply for a low impurity concentration. This disadvantageously leads to an increased device size.
However, the recent demand for miniaturization of the device area has resulted in a tendency to reduce the withstand voltages Veco
1
, Veco
2
for reverse operations, so that the protective diodes D
1
, D
2
must have a diminished series resistance in order to improve their protective effects. To lessen the series resistance, larger devices must be used. Consequently, the size of the diodes D
1
, D
2
becomes substantially equal to that of the transistors Q
1
, Q
2
, which constitute the output section, thereby hindering the size reduction of the output circuit
1
.
Next, the structures of a vertical NPN transistor and a vertical PNP transistor will be described with reference to
FIGS. 2A and 2B
.
FIG. 2A
is a sectional view of a vertical NPN transistor fabricated using a miniaturized process. An N type epitaxial layer
13
is grown on a main surface of a P type semiconductor substrate
11
such as silicon, and a high-concentration buried N
+
impurity diffused region (N
+
BL)
12
(hereafter referred to as a “buried region”) is formed between the semiconductor substrate
11
and the N type epitaxial layer
13
.
An NPN transistor is formed on the buried region
12
. A device isolation region is formed in such a manner as to surround the NPN transistor. The device isolation region is comprised of a high-concentration P
+
impurity diffused region (IsoP
+
) formed in the N type epitaxial layer
13
, and a high-concentration P
+
impurity diffused region (P
+
BL) connected to the P
+
impurity diffused region
14
and extending to an interior of the semiconductor substrate
11
. A P type base region
16
is formed in a device region on a surface of the N type epitaxial layer
13
, the device region being surrounded by the device isolation region.
The P type base region
16
has a depth, for example, of 0.6 &mgr;m from its surface. An N
+
emitter region
17
is formed in the P type base region
16
. The N
+
emitter region
17
has a depth, for example, of 0.3 &mgr;m from its surface. An N
+
high-concentration collector region (DeepN
+
)
18
is formed in a surface region of the N type epitaxial layer
13
at a predetermined distance from the base region
16
so as to connect to the buried region
12
. A base terminal (B) is formed in the P type base region
16
, an emitter terminal (E) is formed in the N
+
emitter region
17
, and a collector terminal (c) is formed in the N
+
high-concentration collector region
18
, respectively, with an N
+
contact region
19
being interposed between the N
+
high-concentration collector region
18
and the collector terminal C.
FIG. 2B
is a sectional view of a vertical PNP transistor formed using the miniaturized process. The same components as in
FIG. 2A
carry the same reference numerals and detailed description thereof is omitted. A P type collector region
20
, an N type base region
21
, and a P
+
emitter region
22
are formed in the N type epitaxial layer
13
, and a collector terminal (C), a base terminal (B), and an emitter terminal (E) are formed in the P type collector region
20
, the N type base region
21
, and the P
+
emitter region
22
, respectively.
Based on correspondence to the sectional structure of the vertical NPN transistor shown in
FIG. 2A
, a N type buried region is formed under the P type collector region
20
, and at the same time a structure connecting to the N type buried region is formed which corresponds to
18
,
19
in FIG.
2
A. These components, however, are not directly relate to the present invention and have thus been omitted.
The value of an emitter-collector withstand voltage Veco of a bipolar transistor is determined by means of a reverse biased emitter junction, that is, when a leakage current arising from avalanche breakdown of a junction formed in a boundary between an emitter and a base regions of the bipolar transistor is conveyed to an interior of the base region, where it becomes an effective base current.
Accordingly, even in a base open state, an amplifying effect substantially equal to the flow of an effective base current occurs in the bipolar transistor, thereby reducing the value Veco below the breakdown voltage of the single reverse biased emitter junction (collector open emitter-base breakdown voltage Vebo), if the reverse current gain &bgr;
R
of the bipolar transistor is larger than 1.
The meaning of the reverse current gain is as follows.
The ratio of the collector current to the base current through the bipolar transistor is a quantity generally called a current gain &bgr;. However, in a circuit involving reversal of the potentials of a collector and emitter of a bipolar transistor (this is hereafter referred to as a reverse operation), the current gain &bgr; of the usual forward biased operation is changed to the current gain &bgr;
R
of the reverse operation.
The current gain &bgr;
R
in present s

Affiliated with

Also associated with

Rating

Semiconductor output circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor output circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor output circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2881201