Semiconductor optical device and optoelectronic integrated...

Active solid-state devices (e.g. – transistors – solid-state diode – Incoherent light emitter structure – In combination with or also constituting light responsive...

Reexamination Certificate

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C257S083000, C257S084000, C257S190000

Reexamination Certificate

active

06355945

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor optical devices using compound semiconductors, and more particularly, to an optoelectronic integrated circuit device (OEIC device) which has an electronic circuit section and an optical circuit section on a GaAs substrate and performs interconnection (mutual conversion) between electrical signals and optical signals in a light-emitting layer composed of a compound semiconductor.
2. Description of the Related Art
OEIC devices including monolithic integration of electronic circuit sections and optical circuit sections on one substrate are under consideration as key devices for broad-band, massive optical communication.
In the configuration of an optoelectronic integrated circuit device which has been recently studied, a GaN light-emitting layer emitting blue short-wavelength light is formed on a GaAs substrate for performing interconnection between electrical signals and optical signals in the light-emitting layer.
When the GaN light-emitting layer is formed on the GaAs substrate, the following problems arise. When a GaN film having high crystallinity which can be used as a light-emitting device is formed, a significantly high deposition temperature is required due to physical properties thereof. When the film is formed by a MOCVD process, which is a most conventional process, deposition must be performed in a high temperature atmosphere of more than 1,000° C., although the temperature depends on the deposition process.
On the other hand, the GaAs substrate causes so-called “arsenic elimination” at approximately 300° C. or more in which the arsenic component is vaporized from the substrate. The arsenic-eliminated portions form pits and thus many dimples form on the substrate. These dimples significantly deteriorate crystallinity of the GaN film formed on the GaAs substrate. Thus, it is significantly difficult to form a GaN light-emitting layer with high crystallinity on a GaAs substrate at an inevitably high temperature.
Lattice constants of GaAs and GaN are 5.653 Å and 3.180 Å, respectively, and are quite different from each other. By such mismatch in lattice constant, the GaN film formed on the GaAs substrate has many lattice defects, as another problem.
In order to prevent these problems, that is, arsenic elimination and lattice mismatch, a proposed method is to previously form a GaN low-temperature-deposited buffer layer on a GaAs substrate at a low temperature which does not cause arsenic elimination. Since the buffer layer functions as a protective film for preventing arsenic elimination in this method, arsenic elimination does not occur when the subsequent deposition of GaN is performed in a high-temperature atmosphere and a GaN film having high crystallinity can be formed. Determination of the optimized deposition temperature for, and the thickness of, the low-temperature-deposition buffer layer, however, are not always feasible. Thus, a new problem, that is, an unstable deposition process arises.
Accordingly, no OEIC device including a semiconductor light-emitting device formed on a GaAs substrate and in which an electronic circuit section and an optical circuit section are monolithically integrated has been realized.
SUMMARY OF THE INVENTION
The present invention provides an OEIC device including a semiconductor optical device composed of a compound semiconductor formed on a GaAs substrate and monolithic integration of an electronic circuit section and an optical circuit section.
The semiconductor optical device comprises: a GaAs substrate; a light-emitting/light-receiving layer comprising a GaN-based compound semiconductor; and a ZnO film formed between the GaAs substrate and the light-emitting/light-receiving layer.
The optoelectronic integrated circuit device comprises: a GaAs substrate including an electronic circuit processing an electronic signal; a ZnO layer on at least portion of the GaAs substrate; and an optical circuit electrically connected to the electronic circuit and comprising at least one GaN-based compound semiconductor layer on the ZnO layer, wherein the GaN-based compound semiconductor layer either receives or emits an optical signal.
According to the present invention, since the difference in lattice constant between the ZnO film as a buffer layer and GaN-based layer as a light-emitting/light receiving layer is significantly small, the formed GaN based layer has high crystallinity. The ZnO film deposited by the sputtering process is spontaneously a-axis-orientated. Therefore, a ZnO film suitable for a buffer layer can be formed without particular attention in the film deposition process and a stabilized deposition process is achieved. The sputtering process can suppress the film deposition temperature to approximately 200° C. (approximately 300° C. at most). This makes it possible to form the buffer layer without arsenic elimination from the GaAs substrate. The buffer layer is formed by a low-temperature deposition process, so that adverse effects of high temperature on the metallization in the electronic circuit section of the OEIC device can be suppressed. In addition, the ZnO film covers the metallization so as not to be directly exposed to high temperature during the formation of the GaN layer. This also suppress adverse effects of high temperature. An ECR-MBE process enables the formation of the GaN layer at a relatively low temperature, and adverse effects of high temperature can be more suppressed.
For the purpose of illustrating the invention, there is shown in the drawings several forms which are presently preferred, it being understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown.


REFERENCES:
patent: 5889295 (1999-03-01), Rennie et al.
patent: 6023077 (2000-02-01), Iyechika et al.
patent: 3527269 (1986-02-01), None
patent: 3527274 (1987-02-01), None
patent: 19648955 (1997-05-01), None
patent: 09-260290 (1997-10-01), None
English Abstract von JP 057 0173 804 A, JPO & Japio, 1982.
Patent Abstracts of Japan: JP 62-296557 A, E-617, 1988, vol. 12/No. 193; and.
Patent Abstracts of Japan: JP 07254694 A, JPO, 1995.

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