Semiconductor device manufacturing: process – Gettering of substrate – By implanting or irradiating
Reexamination Certificate
2006-01-05
2009-02-03
Smith, Matthew (Department: 2813)
Semiconductor device manufacturing: process
Gettering of substrate
By implanting or irradiating
C438S455000, C438S458000, C438S471000, C438S473000, C438S475000, C438S476000, C438S480000, C438S514000, C438S515000, C438S522000, C438S526000, C438S527000, C438S528000, C438S530000, C438S558000, C438S795000, C438S799000, C438S974000
Reexamination Certificate
active
07485551
ABSTRACT:
The present invention relates to a method of fabricating a semiconductor-on-insulator-type heterostructure that includes at least one insulating layer interposed between a receiver substrate of semiconductor material and an active layer derived from a donor substrate of semiconductor material. The method includes the steps of bonding and active layer transfer. Prior to bonding, an atomic species which is identical or isoelectric with the insulating layer material is implanted in the insulating layer. The implantation forms a trapping layer, which can retain gaseous species present in the various interfaces of the heterostructure, thereby limiting formation of defects on the surface of the active layer.
REFERENCES:
patent: 5953622 (1999-09-01), Lee et al.
patent: 6013563 (2000-01-01), Henley et al.
patent: 6696352 (2004-02-01), Carr et al.
patent: 2002/0187619 (2002-12-01), Kleinhenz et al.
patent: 2002/0190269 (2002-12-01), Atwater, Jr. et al.
patent: 2004/0121558 (2004-06-01), Letertre et al.
patent: 2004/0137698 (2004-07-01), Taraschi et al.
patent: 2004/0171196 (2004-09-01), Walitzki
patent: 2005/0048738 (2005-03-01), Shaheen et al.
patent: 2006/0141746 (2006-06-01), Delattre et al.
patent: 2006/0154445 (2006-07-01), Iwabuchi
patent: 2006/0160327 (2006-07-01), Barna
patent: 1 174 926 (2002-01-01), None
patent: WO 2005/055290 (2005-06-01), None
Malek Maliheh
S.O.I.Tec Silicon on Insulator Technologies
Smith Matthew
Winston & Strawn LLP
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