Semiconductor-on-insulator structure with reduced parasitic capa

Details Semiconductor-on-insulator structure with reduced parasitic capa Semiconductor-on-insulator structure with reduced parasitic capa

1998-11-06

1999-11-30

Ngo, Ngan V.

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

257349, 257350, 257531, 257532, H01L 2900

Patent

active

059947594

ABSTRACT:
In a SOI structure according to the invention, a substrate region directly adjacent and underlying the buried oxide layer is doped with a dopant having a conductivity type opposite that of the substrate. This produces a junction between the doped layer and the substrate. Appropriately biasing this junction creates a depletion layer, which effectively extends the width of the buried oxide layer deep into the substrate, thereby reducing parasitic capacitance in the SOI structure, particularly for inductors, interconnects, and other passive circuit elements. Reducing parasitic capacitance reduces associated substrate losses and RC propagation delays. These benefits become increasingly important at high frequencies encountered in RF wireless communication and high speed digital applications.

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