Semiconductor-on-insulator device having a laterally-graded chan

Details Semiconductor-on-insulator device having a laterally-graded chan Semiconductor-on-insulator device having a laterally-graded chan

1996-01-11

1997-09-23

Niebling, John

Fishing, trapping, and vermin destroying

437 44, 437 45, H01L 21265, H01L 2184

Patent

active

056703899

ABSTRACT:
A silicon-on-insulator semiconductor device (40) having laterally-graded channel regions (23A, 24A) and a method of making the silicon-on-insulator semiconductor device (40). The silicon-on-insulator semiconductor device (40) has a gate structure (16) having sidewalls (19, 21) on a semiconductor layer (12). Lightly doped regions (26A, 27A) extend through an entire thickness of a portion of the semiconductor layer (12) under the sidewalls (19, 21). A laterally-graded channel region (23A) is formed below the gate structure (16) and abutting one (26A) of the lightly doped regions. A source (33) is formed in a first (26A) of the lightly doped regions and a drain region (34) is formed in a second (27A) of the lightly doped regions.

REFERENCES:
patent: 4599118 (1986-07-01), Han et al.
patent: 5185280 (1993-02-01), Houston et al.
patent: 5506161 (1996-04-01), Orlowski et al.
Ghavam G. Shahidi et al. "SOI for Low-Voltage and High-Speed CMOS", Extended Abstracts of the 1994 International Conference on Solid State Devices and Materials, Yokohama, 1994, pp. 265-267, Month Unknown.
G.G. Shahidi et al. "A Room Temperature 0.1 .mu.m CMOS On SOI", 1993 Symposium On VLSI Technology, Digest of Technical Papers, pp. 27-28, May, 1993.
G. Shahidi et al. "SOI For a 1-Volt CMOS Technology and Application to a 512Kb SRAM With 3.5 ns Access Time", IEDM, pp. 33.2.1-33.2.4, Dec. 1993.

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