Semiconductor nonvolatile memory device

Details Semiconductor nonvolatile memory device Semiconductor nonvolatile memory device

1994-05-25

1995-08-29

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular biasing

36518905, 36518907, 365203, G11C 1134

Patent

active

054466903

ABSTRACT:
A semiconductor nonvolatile memory device in which the states of memory cells are determined with respect to each of all data lines in a nonvolatile memory device so as to perform control such as continuation and suspension of programming automatically. Memory cell arrays in which nonvolatile semiconductor memory cells are arranged in an array form, word lines W1 and W2 to which control gates of a plurality of memory cell groups (sectors) are connected in common and data lines to which drains of a plurality of memory cells are connected in common are included, and there are possessed of a precharging circuit, a data hold circuit having a sense amplifier function and a data latch function and a memory cell state detecting circuit for each of said data lines. Reprogramming is made at the same time with respect to memory cells (sector) connected to the same word line. During reprogramming operation, the state of memory cells is read out at the same time with all of the data lines, and continuation and suspension of the reprogramming operation are controlled in the device only based on the information.

REFERENCES:
patent: 5172338 (1992-12-01), Mehrotra et al.
T. Tanaka et al., "A Quick Intelligent Program Architecture for 3V--only NAND-EEPROMs", 1992 Symposium on VLSI Circuits Digest of Technical Papers, pp. 20-21, (1992).

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