Static information storage and retrieval – Floating gate – Particular connection
Patent
1997-11-14
1999-04-27
Le, Vu A.
Static information storage and retrieval
Floating gate
Particular connection
36518511, 36518513, G11C 700
Patent
active
058986162
ABSTRACT:
In order to prevent sub bit line disturbance without leading to an increase in the current required for the write inducing new disturbance-related problems, the semiconductor nonvolatile memory according to the present invention comprises sub bit lines mutually connected in parallel with the drain(s) of the memory cells connected with a plurality of word lines for grouping the memory cells in units of a plurality of word lines, sub bit line selection transistors that connects the sub bit line to the bit line in a manner such that connection thereof can be interrupted, a sub source line connected to the source of the memory cells in a block grouped by the bit lines, and a block selection transistor that connects the sub source line to the source line interruptably. Prior to a write of data into at least an individual memory cell, the sub bit line selection transistors and the block selection transistor involved with one group interlock with each other in order to connect only the sub bit lines and the sub source line corresponding to the selected group to the bit lines and the source line respectively.
REFERENCES:
patent: 4999812 (1991-03-01), Amin
patent: 5185718 (1993-02-01), Rinerson et al.
patent: 5682350 (1997-10-01), Lee et al.
A 3.3 V Only 16mb DINOR Flash Memory; S. Kobayashi, et al.; ULSI Laboratory, Mitsubishi Electric Corporation; 1995; pp. 55-62.
"Memory Array Architecture and Decoding Scheme for 3 V Only Sector Erasable DINOR Flash Memory"; Kobayashi, et al.; IEEE Journal of Solid-State Circuits, vol. 29, No. 4; Apr., 1994; pp. 454-460.
Frank Robert J.
Le Vu A.
OKI Electric Industry Co., Ltd.
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