Semiconductor non-volatile storage

Details Semiconductor non-volatile storage Semiconductor non-volatile storage

2001-09-14

2002-11-12

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185110

Reexamination Certificate

active

06480418

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technology for increasing the speed of reading operations in a semiconductor non-volatile storage, more particularly to an effective technology to be adopted for an electrically rewritable flash memory and a single chip microcomputer incorporating such a flash memory.
2. Description of the Related Art
When connecting memory cells to each other on a memory array provided in a semiconductor non-volatile storage such as a flash memory, a technology for forming main bit and sub bit lines hierarchically will be very effective to reduce the parasitic capacity of each of those bit lines, as well as increase the speed of reading operations.
Such a technology is disclosed in the official gazette of Unexamined Published Japanese Patent Application No.Hei-4-14871. The technology is referred to as a DINOR type memory cell connection, in which bit lines are formed hierarchically. The official gazette of Unexamined Published Japanese Patent Application No.Hei-6-077437 has disclosed an AND memory cell connection in which bit and source lines are formed hierarchically and the official gazette of Unexamined Published Japanese Patent Application No.Hei-7-153857 has disclosed an HICR type memory cell connection in which bit and source lines are formed hierarchically, and further a source line is used commonly by adjacent memory cell groups.
A differential sense amplifying method is also effective for increasing the speed of reading operations in a semiconductor non-volatile storage such as a flash memory. Hereunder, description will be made for how to wire read bit lines (hereafter, to be referred to as data lines) and reference bit lines (hereafter, to be referred to as reference lines) assumed as differential inputs, as well as a conventional technology for generating a current difference (voltage difference) between data line and reference line.
Firstly, there is a well-known example described on pages 260-261 of the digest of technical papers at 1991 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE.
This first well-known example is about memory arrays including a normal memory array to which data lines are connected, as well as memory arrays provided with a dummy bit line used as a dedicated reference line respectively. The sense amplifying method adopted for this first example is none other than a loop-back bit line method. In the loop-back bit line method (sense amplifying method), a differential input is a sense amplifying sensitivity, which, at the reference line side, takes a half voltage of the voltage in the “1” and “0” sense amplifiers of the memory cells used as data lines.
The second well-known example is described on pages 124-125 of the digest of technical papers at 1995 IEEE INTERNALTIONAL SOLID-STATE CIRCUITS CONFERENCE.
In the second well-known example, a differential method is adopted for reading sectors, which is executed as follows. The memory mat uses an open bit line to connect the sense amplifier. Only data lines are pre-charged and the pre-charging level is held according to the information of an object memory cell or the object memory cell is discharged, then a half voltage of the pre-charging voltage is supplied to each bit line at the reference line side. In a random byte reading operation in the same well-known example, in addition to the memory mat, a dummy memory cell is used as a dedicated reference line. A half current of the reference current is flown in the dummy memory cell, thereby obtaining a differential input.
On the other hand, the official gazettes of Unexamined Published Japanese Patent No.Hei-4-14871, No.Hei-6-077437, and No.Hei-7-153857 have disclosed memory cell connection methods for flash memories, in which a transistor SiD-MOS used for connecting a main bit line to a sub bit line, is composed of a transistor that can apply a high voltage. This is because a high voltage is applied to the drain or source terminal of an object memory cell in writing operation, thereby rewriting the threshold level voltage of the memory cell. Consequently, the transistor SiD-MOS can supply only a low current, delaying the appearance of the waveforms of select and non-select signals.
The transistor SiD-MOS connecting both bit and sub bit lines functions (in the on-state) for pre-charging, sensing, and discharging of the bit line, in reading operation.
FIG. 2
shows the waveform of the gate signal SiD (i=0, i=1) of the transistor SiD-MOS connecting both main bit and sub bit lines, as well as the function of the transistor SiD-MOS in reading operation. Since the gate signal SiD drives only transistors SiD-MOS matching in the number of bit lines (a few thousands of bits), the waveform of the SiD signal is smooth both at rising and falling parts. If a sub bit line is pre-charged while the transistor SiD-MOS connecting a main bit line and the sub bit line incompletely, the voltage of the sub bit line rises. In the next read cycle, therefore, a voltage difference is generated between the read bit line and the reference bit line of the differential sense amplifier. This voltage different disables stable and fast read operations. Consequently, the pre-charging must be suspended until the SiD signal is deactivated. The suspended time is thus regarded as an overhead time.
Furthermore, when both main bit and sub bit lines are discharged after sensing, the gate signal SiD of the transistor SiD-MOS is switched to the reverse state. The sub bit line cannot be discharged at this time, however, unless the SiD signal is activated.
Consequently, the gate signal switching time (activated time and deactivated time) of the transistor SiD-MOS is regarded as an overhead time.
The conventional technologies ISSCC91 (pp. 260-261) and ISSCC95 (pp. 124-125) that use a differential sense amplifier respectively has proposed a loop-back bit line method, an open bit line method, and a reference line method. The loop-back bit line method uses a dummy bit line to which a dedicated reference line is connected, in addition to a memory mat. The open line method allows a memory mat to be opened to a sense amplifier using an open bit line. The dedicated reference line method uses a dummy memory cell dedicated to a reference line. However, since the column configuration (Y direction) differs between data line and reference line, a difference is also generated between them with respect to both parasitic capacity and parasitic resistance. In addition, since they use different control signals respectively, timings are also varied between them. Unless both data and reference lines exist in the same memory array, therefore, their noises are varied between them. In addition, since a memory cell is fixed for a reference line, the memory cell is always affected by read disturbance. Those are all factors hindering an increase of the speed of reading from the semiconductor non-volatile.
SUMMARY OF THE INVENTION
Under such the circumstances, it is an object of the present invention to provide a semiconductor non-volatile storage that can read data fast, as well as a data processor incorporating such a semiconductor non-volatile storage in it. Concretely, it is an object of the present invention to provide a semiconductor non-volatile storage allowing memory cells to be connected to each other by forming main bit and sub bit lines hierarchically and using a differential sense amplifier, as well as provide a data processor incorporating such a semiconductor non-volatile storage in it so as to make the read operation faster and faster.
In order to solve the above conventional problems, the semiconductor non-volatile in the embodiment of the present invention is composed so that the storage comprises main bit lines, sub bit lines connected to the main bit lines respectively, memory cell arrays, in each of which a plurality of non-volatile semiconductor memory cells are disposed like an array, wherein each of the memory cells includes a source, a drain, and a control gate and the source-drain path is connected to a sub

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