Semiconductor non-volatile latch device including embedded non-v

Details Semiconductor non-volatile latch device including embedded non-v Semiconductor non-volatile latch device including embedded non-v

1997-04-29

1999-04-06

Hoang, Huan

Static information storage and retrieval

Floating gate

Particular connection

365154, 36518905, G11C 1140

Patent

active

058927123

ABSTRACT:
A bistable non-volatile latch circuit adapted to store a non-volatile binary data state during a program operation, and to assume one of two stable states in response to a power up operation that correspond uniquely to the data state has first and second circuit sections. The first circuit section has a first non-volatile current path with means to set the impedance of the first current path in a non-volatile manner. A first end of the first current path is connected to provide a logic output signal, which represents a binary logic state depending on a voltage applied to the a first signal input node. The set/reset signal to the first current path varies between at least the power source voltage and a program voltage that is negative with respect to the power source voltage. A second circuit section generates an output voltage on a second output node that represents a binary logic state opposite from the output states of the first circuit section. Means are provided for connecting the first circuit section and the second circuit section into a bistable configuration.

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Frohman-Bentchkowsky, "The Metal-Nitrice-Oxide-Silicon(MNOS) Transistor--Characteristics and Applications", Proceedings of the IEEE, vol. 58, No. 8, Aug. 1970.
Donald, et al., "SNOS IK X 8 static Nonvolatile RAM," IEEE Journal of Solid-State Circuits, vol. SC-17, No. 5, Oct. 1982.

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