Semiconductor MOSFET device with offset regions

Details Semiconductor MOSFET device with offset regions Semiconductor MOSFET device with offset regions

1988-04-20

1990-10-02

Mintel, William

357 2311, 357 45, 357 238, 357 234, 357 59, H01L 2712

Patent

active

049611011

ABSTRACT:
In a semiconductor device comprising a plurality of planar high-voltage insulated-gate field-effect transistors in which offset regions are provided in portions of the semiconductor substrate near the junctions of adjacent drain regions and near the substrate surface additional, low impurity concentration offset regions are formed in the semiconductor substrate in such a manner that each low impurity concentration offset region is coupled to a source region and is located between the drain regions of the field-effect transistors adjacent to each other and near the semiconductor surface, whereby reduction of the "on resistance" is achieved without affecting the FET sustaining voltage.

REFERENCES:
patent: 4599576 (1986-07-01), Yoshida et al.
patent: 4603341 (1986-07-01), Bertin et al.
patent: 4721990 (1988-01-01), Kinoshita
patent: 4748489 (1988-05-01), Komatsu
patent: 4774560 (1988-09-01), Coe

Affiliated with

Also associated with

Rating

Semiconductor MOSFET device with offset regions does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor MOSFET device with offset regions, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor MOSFET device with offset regions will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-295133