Semiconductor merged logic and memory capable of preventing...

Details Semiconductor merged logic and memory capable of preventing... Semiconductor merged logic and memory capable of preventing...

2001-01-16

2002-07-09

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Powering

Conservation of power

C365S229000, C365S226000, C365S189090, C365S189110, C327S534000, C327S537000, C327S535000, C327S541000, C327S543000

Reexamination Certificate

active

06418075

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit including a logic and a memory merged therein, and a function of preventing increase in an abnormal electric current on power-up. Particularly, it relates to prevention of the abnormal electric current in a semiconductor integrated circuit of two external power supply scheme.
2. Description of the Prior Art
In a system LSI in which a DRAM and a logic, such as a processor or an ASIC (application specific IC), are merged, by connecting between the DRAM and the logic by using a multiple-bit, such as 128-bit, . . . , or 512-bit, internal data bus, it is possible to achieve a high data rate transmission speed which is about one or two orders of magnitude faster compared with a case to connect them with each other on a printed board. Furthermore, it is possible to reduce the number of pins of external I/O compared with a system configuration including a general-purpose DRAM located outside, and to decrease the parasitic impedance of the I/O line by one order or more. Therefore, such a system LSI can greatly reduce current, and contribute to enhancing of the performance of information processing equipment that processes a large amount of data, such as 3D graphic processing equipment or image and speech processing equipment.
FIG. 18
is a block diagram showing the structure of a general system LSI including a logic and a DRAM merged therein. In the figure, reference numeral
1
denotes a large-scale logic, and numeral
2
denotes external pins of this large-scale logic
1
. Reference numeral
3
denotes an analog core that processes an analog signal, and numeral
4
denotes analog pins of this analog core
3
. Reference numeral
5
denotes a DRAM core connected with the large-scale logic
1
via internal interconnections, for storing data which are needed by the large-scale logic
1
, numeral
6
denotes a test interface circuit (hereafter abbreviated as TIC) that disconnects the large-scale logic
1
from the DRAM core
5
in test mode, numeral
7
-
1
denotes test pins that are connected with the DRAM core
5
by the TIC
6
in test mode, and numeral
7
-
2
denotes a power supply pin via which an external power supply voltage exVDD is supplied to the DRAM core
5
.
In operation, the large-scale logic
1
executes an instructed processing based on an instruction input via the external pins
2
, and outputs the execution result via the external pins
2
. The analog core
3
is connected between the large-scale logic
1
and the analog pins
4
, and performs a processing on analog signals. The processing performed by the analog core
3
includes generation of an internal clock signal using a phase-locked loop (PLL), conversion of an analog signal from outside the chip into an equivalent digital signal using an analog-to-digital converter, conversion of a digital signal from the large-scale logic
1
into an equivalent analog signal using a DAC, etc. The TIC
6
disconnects the large-scale logic
1
from the DRAM core
5
, and connects the test pins
7
-
1
with the DRAM core
5
when the chip is placed in test mode. In test mode, a test is carried out on the DRAM core
5
with a tester connected by way of the test pins
7
-
1
to the chip.
FIG. 14
is a block diagram showing the structure of the DRAM disposed in the prior art semiconductor integrated circuit. In the figure, reference numeral
8
denotes a central control circuit block, numeral
9
denotes a command decoder/control circuit, numeral
10
denotes a row address input buffer/latch/refreshing counter, numeral
11
denotes a row pre-decoder, numeral
12
denotes a column address input buffer/latch, numeral
13
denotes a column pre-decoder, numeral
14
denotes a data I/O controller, numeral
15
denotes an internal power supply voltage generation circuit/self-refresh timer block, numeral
16
denotes a memory array, numeral
17
denotes a sense amplifier band, numeral
18
denotes a row/column local control band, and numeral
19
denotes a data path band.
The central control circuit block
8
latches various external control signals given from outside the block in synchronization with a clock signal CLK, decodes them, and activates two or more internal control signals in response to an internal command specified by the decoded external control signals. The internal power supply voltage generation circuit of the internal power supply voltage generation circuit/self-refresh timer block
15
generates a boosted voltage VPP, a power supply voltage VCCP for peripheral circuits, an array power supply voltage VCCS, a precharge voltage VBL, a cell plate voltage VCP, and a substrate voltage VBB.
FIG. 19
is a block diagram showing the structure of such a prior art internal power supply voltage generation circuit. In the figure, reference numeral
20
denotes a level shifter, numeral
21
denotes a VBB generation circuit, numeral
22
denotes a reference voltage generation circuit, numeral
23
denotes a VCCS generation circuit (hereafter abbreviated as VDCS), numeral
24
denotes a VBL/VCP generation circuit, numeral
25
denotes a VPP generation circuit, and numeral
26
denotes a VCCP generation circuit (hereafter abbreviated as VDCP). Each of the VBB generation circuit
21
, the VDCS
23
, the VPP generation circuit
25
, and the VDCP
26
has an active circuit with a large current-feed ability and a standby circuit with a small current-feed ability in parallel.
In the internal power supply voltage generation circuit, to maintain the voltage levels of the plurality of internal power supplies during the standby period of the DRAM, the standby circuits of the VBB generation circuit
21
, the VDCS
23
, the VPP generation circuit
25
, and the VDCP
26
are always activated.
When the decoded control signals associated with an internal command issued indicate row activation, the active circuits of the VBB generation circuit
21
, the VDCS
23
, the VPP generation circuit
25
, and the VDCP
26
are activated according to an ACTOR signal issued by the command decoder/control circuit
9
.
The VDCS
23
is provided with a VCCS abnormality detector for always monitoring the array power supply voltage VCCS, and when the voltage decreases abnormally, raises its output signal from a “Low” level to a “High” level. Furthermore, the VDCP
26
is provided with a VCCP abnormality detector for always monitoring the power supply voltage VCCP, and when the voltage decreases abnormally, raises its output signal from a “Low” level to a “High” level. Similarly, the VPP generation circuit
25
is provided with a VPP abnormality detector for always monitoring the boosted voltage VPP, and when the voltage decreases abnormally, raises its output signal from a “Low” level to a “High” level. As a result, the active circuits of the VDCS
23
, the VPP generation circuit
25
, and the VDCP
26
are activated respectively. When the voltage of one above-mentioned internal power supply generated decreases abnormally even during the standby period, a corresponding active circuit within the VDCS
23
, the VPP generation circuit
25
, or the VDCP
26
receives the output signal of a corresponding abnormality detector, and is then activated. Thus, the internal power supply voltage generation circuit can thus recover the abnormally-decreased voltage of an internal power supply to its normal value by activating a corresponding active circuit.
As shown in
FIG. 15
, the memory array
16
is divided into a number of submemory arrays (SMA)
27
. Two subword driver bands (SWD)
28
and two sense amplifier bands (S/A)
29
are arranged around each of the plurality of submemory arrays
27
. A plurality of main word lines
30
are arranged in a series of two or more submemory arrays
27
arranged in a row so that they extend in the row and are across the two or more submemory arrays
27
. Two or more subword lines
32
are connected with each main word line
30
by way of subword drivers
31
. Each main word line
30
is driven by a main word driver (MWD)

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