Semiconductor memory with wordline timing

Details Semiconductor memory with wordline timing Semiconductor memory with wordline timing

2001-06-14

2004-09-07

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189030, C365S189080, C365S230030, C365S230060, C365S193000, C365S194000, C365S195000

Reexamination Certificate

active

06788614

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to semiconductor memory devices, and more specifically to wordline timing in semiconductor memory devices.
BACKGROUND OF THE INVENTION
Semiconductor memory devices such as dynamic random access memory (DRAM) devices are widely used in computers and other electronic devices. As the speed of such electronic devices increases, it is important that the speed of accessing data stored in the memory devices also increases or at least does not decrease as the density of the memory devices increases so that the electronic devices do not have to wait for data. Memory access speeds continue to increase as electronic device require greater amounts of data at increased delivery rates. Access speeds to DRAM devices are approaching 250 MHz and above. However, access speed may be limited by timing of memory access with other functions in the electronic device. The windows of time during which the memory is accessed decrease as the access speed increases. As a result, the length of time during which the memory device has to access the data stored therein (access window) has been reduced from the order of nanoseconds to picoseconds.
An enhancement of DRAM circuitry is the addition of isolation gates between the digit lines and a sense amplifier. Such isolation gates resistively separate the sense amplifier from the digit line capacitances. As a result, the sense amplifier latches data more quickly. The benefit of isolation gates is more significant for higher density DRAMs, which have longer digit lines, and thus higher digit line capacitances.
The isolation gates are controlled by a control signal which must be accurately timed in relation to other DRAM signals, such as the signal that activates the sense amplifier. There is a continuing need to supply DRAMs with greater memory capacity. As a result, the length of isolation gate control signal lines have increased. Accordingly, isolation signals experience an RC delay as the signals travel through the signal lines. If the timing of the control signal and other memory device signals are inaccurately timed, the sense amplifier may not operate as desired and errors will occur in reading the data from the memory device. Therefore, there is a need for a method to reduce timing inaccuracy and improve access speeds of DRAMS.
SUMMARY OF THE INVENTION
The above mentioned problems with memory devices and electronic devices incorporating memory devices therein, and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
Embodiments of the invention include a timing circuit linking activation of a memory decoder to a change of state of a control signal adjacent the memory array connected to the memory decoder. The timing circuitry reduces timing inaccuracies in accessing a selected memory location in the memory array.
In one embodiment, the timing circuitry is associated with a memory decoder, receives the control signal, and in response thereto activates the memory decoder to access select memory cells in the memory array. In another embodiment, the timing circuitry is associated with a wordline decoder. In another embodiment, the timing circuitry is connected to the isolation gate signal line adjacent a sense amplifier bank so as to reduce the effects of control signal propagation delay. In another embodiment, the timing circuitry receives both an isolation gate control signal and another signal thereby controlling memory access based on two inputs.
A further embodiment of the invention is a method for controlling a decoder based on a control signal for the isolation transistors.
Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with reference to the accompanying drawings.


REFERENCES:
patent: 4571705 (1986-02-01), Wada et al.
patent: 5132931 (1992-07-01), Koker
patent: 5313431 (1994-05-01), Uruma et al.
patent: 5335206 (1994-08-01), Kawamoto
patent: 5392241 (1995-02-01), Butler et al.
patent: 5410508 (1995-04-01), McLaury
patent: 5459846 (1995-10-01), Hyatt
patent: 5612918 (1997-03-01), McClure
patent: 5646898 (1997-07-01), Manning
patent: 5790462 (1998-08-01), McClure
patent: 5838990 (1998-11-01), Park et al.
patent: 5970022 (1999-10-01), Hoang
patent: 5999480 (1999-12-01), Ong et al.
patent: 6028805 (2000-02-01), Higuchi
patent: 6084811 (2000-07-01), Dorney
patent: 6091659 (2000-07-01), Watanabe et al.
patent: 6107134 (2000-08-01), Lu et al.
patent: RE37176 (2001-05-01), Kajigaya et al.
patent: 6295593 (2001-09-01), Hsu et al.
patent: 6333869 (2001-12-01), Tanizaki et al.
patent: 6349072 (2002-02-01), Origasa et al.
patent: 6366515 (2002-04-01), Hidaka
patent: 2002/0000837 (2002-01-01), Keeth et al.

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