Semiconductor memory with transfer buffer structure

Details Semiconductor memory with transfer buffer structure Semiconductor memory with transfer buffer structure

2000-03-16

2001-04-17

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S051000, C365S063000

Reexamination Certificate

active

06219295

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory having an overlaid bus structure and a control circuit for the same.
Recent demands for reduction in the number of parts of apparatuses associated with a trend toward portable apparatuses, reduction in power consumption, and higher speed and expanded bit widths for improved data transfer efficiency have resulted in an increased need for the so-called memories combined with logic wherein memories of various capacities and configurations are combined with logic systems performing various kinds of data processing into a single IC chip.
In most cases, a bus for exchanging data between a memory portion and a logic portion has a constant width, e.g., 64 or 128 bits. In order to satisfy various requirements of such systems mixed with a logic portion or the like, it is desirable that a memory portion is configured to have a data bus width which remains unchanged irrespective of changes in an address configuration or memory capacity.
In order to satisfy such a need, memory systems having an overlaid bus structure have been proposed.
FIG. 16
shows a circuit configuration of memory cell arrays of a memory system having an overlaid bus structure and a peripheral portion of the same.
FIG. 16
focuses on three memory cell arrays among a plurality of memory cell arrays which constitute a memory system. The memory system shown in
FIG. 16
employs a shared sense amplifier system in which a sense amplifier is shared by memory cells in adjoining memory cell arrays.
The memory system is formed by memory cell arrays MCAi−1, MCAi, and MCAi+1, data line pairs DATA
0
through DATA
255
shared by the memory cell arrays, sense amplifiers S/A and S/A
1
through S/A
4
, column switches CSW, CSW
1
, and CSW
2
, and a decoder circuit DEC. Each memory cell array has 256 lines and 1024 columns and has 1024 bit line pairs and 256 word lines which are not shown.
FIG. 16
shows only bit lines pairs BL and BL
1
through BL
4
. The sense amplifiers S/A and S/A
1
through S/A
4
are shared by adjoining memory cell arrays. For example, the sense amplifier S/A
1
is shared by the memory cell arrays MCAi and MCAi−1, and the sense amplifier S/A
2
is shared by the memory cell arrays MCAi and MCAi+1.
BL
1
through BL
4
of the memory cell array MCAi are connected to sense amplifiers S/A
1
through S/A
4
, respectively. The sense amplifiers S/A
1
and S/A
3
are connected to the data line pair DATA
0
through. the columns switch CSW
1
, and the sense amplifiers S/A
2
and S/A
4
are connected to the data line pair DATA
0
through the column switch CSW
2
. Therefore, the four sense amplifiers S/A
1
through S/A
4
of the memory cell array MCA
1
can be connected to the pair of data lines DATA
0
. That is, each memory cell array has a common data line pair for every four bit lines. Although not shown, since a memory cell array has 1024 bit line pairs, there are 1024/4=256 pairs of data lines DATA. The operation of this memory system will be described below with reference to an example wherein data on the memory cell array MCAi are read on the data line pairs DATA
0
through DATA
255
.
According to a row address, the decoder circuit DEC selects one word line of the desired memory cell array MCAi. The data on the bit line pairs BL
1
through BL
4
designated by the selected word line are transmitted to the sense amplifiers S/A
1
through S/A
4
to activate MCAi. Further, when the sense operation of the sense amplifiers S/A
1
through S/A
4
is complete, the decoder circuit DEC controls turning on/off of the column switches CSW
1
and CSW
2
according to a column address to transmit the data sensed and held by one of the sense amplifiers S/A
1
through S/A
4
to the data line pair DATA
0
. Thus, the data in the memory cell selected according to the column address on the word line selected according to the row address are transmitted to the data line pair DATA
0
. Since data are similarly transmitted to the data line pairs DATA
1
through DATA
255
, data are transmitted to 256 pairs of data lines in total.
FIG. 17
shows a configuration of a memory system with a data bus having a width of 128 I/O as an example of a memory system utilizing the above-described overlaid structure.
The memory system is formed by two blocks
1701
and
1702
which are each formed by sixteen memory cell arrays MCA
0
through MCA
15
and MCA
16
through MCA
31
, respectively. Each of the memory cell arrays has 256 rows and 1024 columns, which means that the total capacity of the memory system is 8 megabit.
There are groups of data lines
1704
and
1705
each consisting of 256 data lines which can be connected to the memory cell arrays MCA
0
through MCA
15
and MCA
16
through MCA
31
, respectively, in the direction of the bit lines of the memory cell arrays. The groups of data lines
1704
and
1705
are connected to column decoders
1706
and
1707
, respectively. A decoder circuit
1703
is provided between the blocks
1701
and
1702
and is shared by those blocks to control the selection of word lines and column switches in each of the blocks simultaneously.
The decoder circuit
1703
selects arbitrary word lines of, for example, the memory cell arrays MCA
5
and MCA
21
according to a row address input thereto. The data on the selected word lines are transmitted to the sense amplifier to be sensed (memory cell arrays MCA
5
and MCA
21
are activated). Next, the decoder circuit
1703
selects the sense amplifier according to a column address input thereto to transmit the data to the groups of data lines
1704
and
1705
. The groups of data lines
1704
and
1705
are connected to the column decoders
1706
and
1707
, respectively. The column decoders
1706
and
1707
select 64 data lines from among the respective 256 data lines and connect them to data buses
1708
and
1709
, respectively.
As described above, there are upper and lower data buses of 64 I/O each which provide an overall bus width of 128 I/O.
The capacity of a memory system having such a structure can be increased or decreased by increasing or decreasing the number of memory cell arrays MCA. However, this will not increase or decrease the number of the data lines. It is therefore possible to always maintain a constant data bus width.
A description will now be made on a case wherein data are read from the memory cell arrays MCA
13
and MCA
29
after the data in the memory cell arrays MCA
5
and MCA
21
are read.
First, the data in the memory cell arrays MCA
5
and MCA
21
are read according to the procedure described above. Next, the decoder circuit resets and precharges the memory cell arrays MCA
5
and MCA
21
which have been in an activated state. Then, the decoder circuit
1703
selects arbitrary word lines of the memory cell arrays MCA
13
and MCA
29
according to a row address input thereto. The data on the selected word lines are transmitted to the sense amplifier to be sensed (memory cell arrays MCA
13
and MCA
29
are activated). Next, the decoder circuit
1703
selects the sense amplifier according to a column address input thereto to transmit the data to the groups of data lines
1704
and
1705
. The data on the groups of data lines
1704
and
1705
are input to the column decoders
1706
and
1707
, respectively. The column decoders
1706
and
1707
select 64 data lines from among the respective 256 data lines and connect them to data buses
1708
and
1709
, respectively.
As described above, the memory cell arrays are activated and precharged according to the row addresses decoded by the decoder circuit
1703
. Therefore, the operation of reading the data in the different memory cell arrays proceeds in a sequence such that the memory cell arrays MCA
5
and MCA
21
are activated; the data are read from the same; the memory cell arrays MCA
5
and MCA
21
are reset and precharged; the memory cell arrays MCA
13
and MCA
29
are activated; and then the data are read from the same. Thus, the operations of activating, resetting and precharging a memory

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