Semiconductor memory with static column decode and page mode add

Details Semiconductor memory with static column decode and page mode add Semiconductor memory with static column decode and page mode add

1985-08-07

1988-06-14

Hecker, Stuart N.

Static information storage and retrieval

Addressing

Sync/clocking

365241, 365230, G11C 800

Patent

active

047508396

ABSTRACT:
A semiconductor memory includes a memory array (10) that is operable to be addressed in either the page mode or the static column decode mode. A column address transparent latch (20) is provided which is controlled to either directly input a column address to a column decoder (26) or to latch the address in response to the generation of the column address strobe. A sequence detect circuit (30) detects the sequence to the row address strobe and the column address strobe to determine whether the page mode or the static column decode mode is generated. The sequence detect circuit (30) generates a Y-enable signal in a circuit (31) for control of the latch (20).

REFERENCES:
patent: 4079462 (1978-03-01), Koo
patent: 4303993 (1981-12-01), Panepinto, Jr. et al.
Davis et al, "Memory Decode Architecture", IBM Tech. Disc. Bull., vol. 27, No. 4A, Sep. 1984, pp. 2290-2291.

Affiliated with

Also associated with

Rating

Semiconductor memory with static column decode and page mode add does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory with static column decode and page mode add, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory with static column decode and page mode add will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-502377