Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2000-08-22
2002-02-19
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S208000, C257S659000, C438S454000
Reexamination Certificate
active
06348722
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor memory, and more particularly to a semiconductor memory in which noises between wiring layers are prevented to enhance read and write speeds.
2. Description of the Related Art
Semiconductor memories such as a static random access memory (SRAM) have parasitic capacitance. The parasitic capacitance includes substrate capacitance between a substrate and wiring on the substrate, interlayer capacitance formed between RAM macro wiring and over-macro through wiring, and lateral capacitance caused between wires. The substrate capacitance and the interlayer capacitance are extremely high as compared with the lateral capacitance.
In recent years, the concept of lateral capacitance is changing as devices are getting finer. That is, with increasing fineness, wiring decreases in area component to lower interlayer capacitance which is proportional to the area of the wiring, whereby lateral capacitance forms an increasing proportion of the parasitic capacitance.
Conventionally, such lateral capacitance and other stray capacitance, or electric capacitances at portions other than required, have been taken into account through the optimizations of transistor size and wiring arrangement.
For example, Japanese Patent No. 2751591 discloses a method of fabricating a semiconductor memory device for reducing the stray capacitance of a dynamic random access memory (DRAM) to improve characteristics including responsivity (prior art
1
).
FIGS. 1 and 2
are top views of semiconductor memory devices described in the prior art
1
. As shown in
FIG. 1
, bit lines
101
of low specific resistance polycrystalline silicon, aluminum, or the like are formed parallel to one another on a semiconductor substrate (not shown) by chemical-vapor deposition (CVD) or sputtering. Formed over the bit lines
101
is an interlayer insulation film
102
. The interlayer insulation film
102
is subjected to inert gas such as N
2+
and He
+
with a dose of the order of 10
14
to 10
15
cm
−2
or higher for ion implantation. Some of the gas molecules are not dissolved into the interlayer insulation film
102
completely, and remain inside the interlayer insulation film
102
as bubbles, forming a plurality of fine cavities. On this interlayer insulation film
102
is formed a shield conductive layer
104
having openings
103
of stripe configuration along the direction orthogonal to the bit lines
101
. This shield layer
104
is a (½) VDD (power supply) layer formed of, e.g., the same polycrystalline Si or the like as that of the bit lines. This shield layer absorbs electrostatic induction caused between the bit lines.
In
FIG. 2
, an interlayer insulative film
102
having fine cavities is formed as described above. Then, a conductive layer is formed thereon. Furthermore, the conductive layer is provided with openings
105
to form a shield conductive layer
106
having a mesh-like pattern.
Such formation of a plurality of fine cavities inside the interlayer insulation film can substantially lower the relative permittivity of the insulation layer in between the bit lines and the shield conductive layer. Moreover, the provision of openings in the shield conductive layer can reduce the area for the shield conductive layer to overlap with the bit lines. This allows a reduction of the capacitance between the bit lines and the shield conductive layer.
Moreover, some SRAMs with reduced spacings between wires and between wiring layers for higher integration have a shield layer between the wiring layers so that noises from the wiring passing over a RAM are prevented from causing the internal wiring of the RAM to malfunction (prior art
2
).
FIG. 3
is a perspective view showing an SRAM in the prior art
2
.
FIGS. 4 and 5
are views showing the SRAM of the prior art
2
.
FIG. 4
is a bottom view showing how the shield layer and the RAM macro wiring shown in
FIG. 3
overlap with each other.
FIG. 5
is a schematic diagram showing the interlayer capacitance between the shield layer and the RAM macro wiring in a cross section along the RAM macro wiring shown in FIG.
3
. As shown in
FIG. 3
, a shield layer
11
consisting of an Al full layer is formed between RAM macro wiring
1
and over-macro through wiring
3
above, which lies above the RAM macro wiring
1
and passes over the RAM macro. The RAM macro wiring
1
and the over-macro through wiring
3
must not interfere with each other in operation, for the interference would cause a RAM malfunction. The shield layer
11
is thus formed all over the RAM macro, whereby the RAM macro wiring
1
inside the RAM can be prevented from the influence of the noises caused by the over-macro through wiring
3
, so as to avoid a RAM malfunction.
Nevertheless, while the shield layer in the prior art
1
absorbs the capacitance appearing between bit lines by dissipating electric lines of force extending between the bit lines therethrough, no consideration is given to noises appearing between wiring layers. Besides, finer wiring makes a reduction in the wiring are to lower the interlayer capacitance between wiring layers, whereas that interlayer capacitance still forms a major proportion of all interlayer capacitances. In the prior art
1
, the shield layer is provided with openings so that the overlapping area of the shield layer and the bit lines decreases to reduce the interlayer capacitance between the bit lines and the shield layer, which is proportional to the size of the area. This, however, leaves a problem in that the parasitic capacitance other than that between the bit lines and the shield conductive layer cannot be reduced.
Moreover, the shield layer in the prior art
2
has the problem that the interlayer capacitance between the RAM macro wiring and the shield layer is extremely high.
As seen from above, wires are under various types of parasitic capacitance, and in even finer wiring, the capacitance appearing between macro wiring and a substrate and the interlayer capacitance appearing between the macro wiring layer and another layer occupy great proportions as compared with the wire-to-wire capacitance caused between wires. While reductions have been conventionally made on the wire-to-wire capacitance caused between wires, no sufficient measures are taken against interlayer capacitance heretofore. The reduction in interlayer capacitance, if made possible, would allow higher levels of semiconductor devices, which extremely advantageously enables higher integration of semiconductor devices within limited specifications. This interlayer capacitance, however, has heretofore remained as the factor to preclude the higher integration of semiconductor devices.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a fast-response semiconductor memory which can avoid noises from over-macro through wiring affecting macro wiring and reduce the parasitic capacitance appearing on the macro wiring as well.
A semiconductor memory according to the present invention comprises a shield layer between macro wiring inside a macro and through wiring over the macro. The shield layer has a plurality of conductive layers arranged parallel to each other at a pitch of W
1
, the conductive layers extending in a direction orthogonal to the macro wiring. The pitch W
1
of the conductive layers is equal to or smaller than P
1
, where P
1
is a pitch of the conductive layers at which the interlayer capacitance between the macro wiring and the shield layer becomes equal to the interlayer capacitance between the macro wiring and the over-macro through wiring.
Another semiconductor memory according to the present invention comprises a mesh-like shield layer between macro wiring inside a macro and through wiring over the macro. The shield layer has a plurality of openings each having an opening width of W
2
along the longitudinal direction of the macro wiring. The opening width W
2
is equal to or smaller than P
2
, where P
2
is an opening width at which the interlayer capacit
Chaudhuri Olik
Hutchins, Wheeler & Dittmar
Nguyen DiLinh P.
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