Semiconductor memory with multiple wordline selection

Details Semiconductor memory with multiple wordline selection Semiconductor memory with multiple wordline selection

2009-09-22

2011-11-29

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230010, C365S191000, C365S207000, C365S230080

Reexamination Certificate

active

08068382

ABSTRACT:
A semiconductor memory circuit, comprising: a memory array, the memory array including a plurality of wordlines each connected to a respective row of cells and a plurality of bitlines each connected to a respective column of cells. The semiconductor memory circuit also comprises at least one row decoder for selecting a group of wordlines within the plurality of wordlines; and a plurality of driver circuits for driving the plurality of bitlines respectively and setting the cells connected to the group of wordlines to a predetermined logic state. Also, a method for presetting at least part of a memory array, the memory array comprising a plurality of wordlines each connected to a respective row of cells. The method comprises selecting a group of wordlines within the plurality of wordlines; and simultaneously setting memory cells connected to the group of wordlines to a predetermined logic state.

REFERENCES:
patent: 4802129 (1989-01-01), Hoekstra et al.
patent: 5802555 (1998-09-01), Shigeeda
patent: 5953538 (1999-09-01), Duncan et al.
patent: 6944093 (2005-09-01), Sumitani
patent: 7505295 (2009-03-01), Nataraj et al.
patent: 7533222 (2009-05-01), Leung
patent: 7599975 (2009-10-01), Donovan et al.
patent: 7742334 (2010-06-01), Fujisawa et al.
patent: 2010/0157715 (2010-06-01), Pyeon
patent: 2010/0161877 (2010-06-01), Pyeon
Written Opinion of the International Searching Authority mailed on Apr. 19, 2010 in connection with International Patent Application PCT/CA2009/001860, 4 pages.
International Search Report mailed on Apr. 19, 2010 in connection with International Patent Application PCT/CA2009/001860, 5 pages.
Notice of Allowance and Fee(s) Due issued by the United States Patent and Trademark Office on Jun. 10, 2011 in connection with U.S. Appl. No. 12/337,841, 9 pages.

Affiliated with

Also associated with

Rating

Semiconductor memory with multiple wordline selection does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory with multiple wordline selection, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory with multiple wordline selection will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4289174