Semiconductor memory with multiple clocking for test mode entry

Details Semiconductor memory with multiple clocking for test mode entry Semiconductor memory with multiple clocking for test mode entry

1990-08-17

1992-11-03

Beausoliel, Robert W.

Excavating

371 211, 324158R, G06F 1100

Patent

active

051611597

ABSTRACT:
An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode, is disclosed. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device. Acknowledgment of the entry into test mode is provided by the presentation of a low impedance at output terminals while the device is not enabled; chip enable of the device causes the device to exit the test mode. Once in test mode, the output enable terminal of the device can provide a chip enable function.

REFERENCES:
patent: 4398146 (1983-08-01), Draheim
patent: 4654849 (1987-03-01), White, Jr. et al.
patent: 4771407 (1988-09-01), Takemae et al.
patent: 4841233 (1989-06-01), Yoshida
patent: 4860259 (1989-08-01), Tobita
patent: 4970727 (1990-11-01), Miyawaki
patent: 5019772 (1991-05-01), Dreibelbis
patent: 5036272 (1991-07-01), Cho
McAdams, et al., "A 1-Mbit CMOS Dynamic RAM With Design-For Test Functions", IEEE Journal of Solid-State Circuits (Oct. 1986), vol. SC-21, No. 5, pp. 635-642.
Shimada, et al., "A 46-ns 1-Mbit CMOS SRAM", IEEE Journal of Solid-State Circuits (Feb. 1988), vol. 23, No. 1, pp. 53-58.

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