Semiconductor memory with memory unit comprising a plurality of

Static information storage and retrieval – Addressing – Plural blocks or banks

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360 51, G11C 800

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active

052048420

ABSTRACT:
An AND type read-only memory (D-A-ROM), includes a memory unit divided into blocks in a row direction and into sub-blocks a column direction, a Y decoder, an X decoder and a column selector. An output of the Y decoder and an output of the X decoder are connected to the memory blocks by first and second gate electrode connectors, respectively. A read control signal from the CPU is connected to each of the memory blocks by third gate electrode connectors. In addition, the output of the X decoder is supplied in parallel to each of the memory sub-blocks through bypass connectors including aluminum interconnections of a separately formed second layer. The read control signal is supplied in parallel to each of the memory sub-blocks through bypass interconnections of the second layer.

REFERENCES:
patent: 4638458 (1987-01-01), Itoh
patent: 4675845 (1987-06-01), Itoh et al.
patent: 4709351 (1987-11-01), Kajigaya
patent: 4782465 (1988-11-01), Uchida
IBM Technical Disclosure Bulletin vol. 18 No. 10 Mar. 1976 Array Row Driver NPN Transistor, Battista et al.
Electronics (Jun. 2, 1982) Asynchronous Circuits Accelerate Access to 256-K Read-Only Memory, Scherpenberg et al.
IBM Technical Disclosure Bulletin vol. 17 No. 1 Jun. 1974 Memory System Fabrication Using Laser Formed Connections, Cook et al.
Kouyama, S. et al.: Very High Speed MOS Device, Japan, Feb. 10, 1986, pp. 316-318.

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