Static information storage and retrieval – Addressing
Reexamination Certificate
2000-04-05
2001-05-22
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
C365S230040
Reexamination Certificate
active
06236614
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to semiconductor memories and, more specifically, to semiconductor memories in which local phase signals are generated in local phase drivers using global phase signals and local isolation signals, thus eliminating the need to route section signals to the local phase drivers.
2. State of the Art
As shown in
FIG. 1
, a conventional Dynamic Random Access Memory (DRAM)
10
includes multiple 256 Kilobit (KB) sub-arrays
12
accessed using even and odd row decoders
14
and
16
, sense amplifiers
18
, gap circuitry
20
, center circuitry
22
, and address circuitry
24
. More specifically, accessing one of the sub-arrays
12
begins when the address circuitry
24
receives a memory address (not shown) and outputs section signals SECTION, global isolation signals GISO, and global phase signals GPH in response. Referring to
FIG. 2
for a moment, the center circuitry
22
receives the section signals SECTION and the global isolation signals GISO and gates them together in local isolation (LISO) circuitry
26
to produce local isolation signals LISO. Referring now to
FIG. 3
, the gap circuitry
20
receives the section signals SECTION and the global phase signals GPH and gates them together in local phase drivers
28
to produce local phase signals LPH. The local phase signals LPH are then used in conjunction with the memory address (not shown) by one of the row decoders
14
and
16
to fire a selected row in one of the sub-arrays
12
. Once the selected row is fired, the local isolation signals LISO are used in one of the sense amplifiers
18
in conjunction with the memory address (not shown) to access a selected column in the same sub-array
12
as the selected row.
As can be seen in
FIG. 1
, many signals must be routed to the gap circuitry
20
and sense amplifiers
18
, including the section signals SECTION, the local isolation signals LISO, and the global phase signals GPH. These signals use “real estate” on the die on which the DRAM
10
is fabricated, and thus limit the functional circuitry that can be implemented in the DRAM
10
, or increase the necessary size of the die on which the DRAM
10
is fabricated. Thus, it would be desirable to reduce the signals routed to the gap circuitry
20
and sense amplifiers
18
in order to increase the functional circuitry that can be implemented in the DRAM
10
or decrease the necessary size of the die on which the DRAM
10
is fabricated.
Therefore, there is a need in the art for a semiconductor memory having a reduced number of signals routed to gap circuitry and sense amplifiers.
SUMMARY OF THE INVENTION
A semiconductor memory, such as a Dynamic Random Access Memory (DRAM), in accordance with the invention includes address circuitry for receiving memory addresses and outputting corresponding section signals, global isolation signals, and global phase signals. Local isolation circuitry incorporated, for example, into center circuitry of the semiconductor memory outputs local isolation signals in accordance with the section signals and the global isolation signals. Local phase signal circuitry, such as local phase drivers, outputs local phase signals in accordance with the global phase signals and the local isolation signals. Row accessing circuitry, such as row decoders, activates rows in a memory array of the semiconductor memory that are selected in accordance with the memory addresses and the local phase signals. Column accessing circuitry, such as sense amplifiers, accesses columns in the memory array selected in accordance with the memory addresses using the local isolation signals.
Thus, the local phase signal circuitry uses the local isolation signals in combination with the global phase signals to generate the local phase signals, in contrast to the conventional practice previously described, in which local phase drivers use section signals in combination with the global phase signals to generate the local phase signals. By eliminating the use of the section signals to generate the local phase signals, the invention eliminates the need to route the section signals to the local phase drivers, and thus reduces the die “footprint” of the semiconductor memory.
In other embodiments of the invention, the above described semiconductor memory is incorporated into an electronic system and is fabricated on the surface of a semiconductor substrate, such as a semiconductor wafer.
In still another embodiment of the invention—a method of accessing a memory array in a semiconductor memory—memory addresses are provided to the semiconductor memory, and section signals, global isolation signals, and global phase signals are then generated in accordance with the memory addresses. The section signals and global isolation signals are gated together to generate local isolation signals, and the local isolation signals and global phase signals are then gated together to generate local phase signals. With the local phase signals generated, rows in the memory array selected in accordance with the memory addresses and the local phase signals are activated, and columns in the memory array selected in accordance with the memory addresses are accessed using the local isolation signals.
REFERENCES:
patent: 6104661 (2000-08-01), Waller
Lam David
Micro)n Technology, Inc.
Nelms David
TraskBritt
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