Semiconductor memory with inverted write-back capability and met

Details Semiconductor memory with inverted write-back capability and met Semiconductor memory with inverted write-back capability and met

1990-11-29

1994-02-22

Canney, Vincent P.

Excavating

365201, 371 214, G11C 2900

Patent

active

052894754

ABSTRACT:
An integrated circuit having a memory, and a method of operating the same, which provides for improved test efficiency. The memory includes static random access memory cells which power up in a preferred state; the preferred state draws less standby power, and is less susceptible to noise and other undesired effects which could cause upset of the stored data state. The method of testing the memory includes writing the memory cells with the complement of the preferred data state, so that all memory cells contain the higher current state; measurement of the standby current after the writing of the complement of the preferred data state will thus measure the worst case standby current. The method of testing may also include a disturb test, where the cell under test, or a neighboring cell in an adjacent row, is repeatedly accessed; such disturbing thus performs the worst case test, since the preferred state is more stable than its complement. Circuitry for performing the inverted write-back of the stored contents is also disclosed, so that such write-back may be performed without requiring read and write operations from the external terminals of the circuit.

REFERENCES:
patent: 4251876 (1981-02-01), McKenney et al.
patent: 4288865 (1981-09-01), Graham
patent: 4567389 (1986-01-01), van Tran
patent: 4618785 (1986-10-01), van Tran
patent: 4771407 (1988-09-01), Talemae et al.
patent: 4816757 (1989-03-01), Hutchins
patent: 4820974 (1989-04-01), Katsura et al.
patent: 5079744 (1992-01-01), Tobita et al.

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