Semiconductor memory with interdigitated array having bit line p

Details Semiconductor memory with interdigitated array having bit line p Semiconductor memory with interdigitated array having bit line p

1998-03-10

2000-09-12

Tran, Andrew Q.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523004, 365200, 365 63, G11C 810

Patent

active

061187275

ABSTRACT:
A memory device includes a memory array having bit line pair interface connections being made alternatively at each side of the array. Column redundancy bit line pairs may be directed to either side of the array. In addition, bit line loads are placed at both ends of respective bit line pairs to improve speed. Stated differently, the memory device includes a bit line pair accessible from either of two sides of the memory array. The array may be one of a number of blocks within the memory device, while the bit line pair may comprise a redundant column bit line pair. The two sides of the memory array from which the bit line pair is accessible may be opposite sides of the array. In addition, the memory device may also include interdigitated bit line pairs within the memory array. One or more bit line pairs, including the above-mentioned redundant column bit line pair, may have bit line loads (e.g., transistors) at each end.

REFERENCES:
patent: 4982372 (1991-01-01), Matsuo
patent: 5036491 (1991-07-01), Yamaguchi
patent: 5060200 (1991-10-01), Miura et al.
patent: 5841687 (1998-11-01), Rees
"A 15ns 16Mb CMOS SRAM with Reduced Voltage Amplitude Data Bus", Masato Matsumiya Shoichiro Kawashima, Makoto Sakata, Toru Miyabo, Toru Koga, Kazuo Itabashi, Kazuhiro Mizutani, Taiji Ema, Kazuhiro Toyoda, Takashi Yabu, Hiroshi Shimada, Noriyuki Suzuki, Masahiko Ookura, ISSCC 92/Session 13/Static RAMS/Paper 13.5, 1992 IEEE International Solid-State Circuits Conference, p. 214-215, 287.
"A 45ns 16Mb DRAM with Triple-Well Structure", Syuso Fujii, Masaki Ogihara, Mitsuru Shimizu, Munehiro Yoshida, Kenji Numata, Takahiko Hara, Shigeyoshi Watanabe, Shizuo Sawada, Tomohisa Mizuno, Junpei Kumagai, Susumu Yoshikawa, Seiji Kaki, Yoshikazu Salto, Hideaki Aochih, Takeshi Hamamoto, Ko-ichi Toita, ISSCC 89/Friday Feb. 17, 1989/East Grand Ballroom, 1989 IEEE International Solid-State Circuits Conference, p. 248-249.

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