Semiconductor memory with inter-block bit wires and...

Details Semiconductor memory with inter-block bit wires and... Semiconductor memory with inter-block bit wires and...

2005-01-25

2005-01-25

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S104000, C365S204000, C365S185160, C257S390000

Reexamination Certificate

active

06847577

ABSTRACT:
A memory cell array is composed of a plurality of blocks separated in column direction every three word lines. Inter-block bit wires are arranged. Each inter-block bit line connects a middle diffusion wire for one of the memory cell units of first block of the separated blocks and the middle diffusion wire for one of the memory cell units of the adjacent second block lying on the other end side of the diffusion wires of the first block. Inter-block ground wires are arranged. Each inter-block ground wire connects the boundary diffusion wire for the one memory cell unit of the first block and the boundary diffusion wire for the one memory cell unit of the adjacent third block lying on the one end side of the diffusion wires of the first block.

REFERENCES:
patent: 5392233 (1995-02-01), Iwase
patent: 5671173 (1997-09-01), Tomita
patent: 5-167042 (1993-07-01), None

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