Semiconductor memory with edge transition detection pulse disabl

Details Semiconductor memory with edge transition detection pulse disabl Semiconductor memory with edge transition detection pulse disabl

1994-02-28

1996-02-20

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

365218, 36523006, G11C 800

Patent

active

054935377

ABSTRACT:
A system and method are provided for disabling the edge transition detection circuit during the flash clear cycle, thereby preventing the generation of an edge transition detection pulse. In a preferred embodiment of the invention, the edge transition detection circuit is connected to the flash clear complement circuitry through a logic gate. During the flash clear cycle, flash clear true, FC.sub.T, is pulled high, flash clear complement, FC.sub.c, is pulled low and inverted to drive a portion of the ETD circuitry high, thereby preventing generation of an ETD pulse during the flash clear cycle.

REFERENCES:
patent: 4872143 (1989-10-01), Sumi
patent: 4891793 (1990-01-01), Anami
patent: 4922461 (1990-05-01), Hayakawa et al.
patent: 5047985 (1991-09-01), Miyaji
patent: 5124584 (1992-06-01), McClure
patent: 5243575 (1993-09-01), Sambandan et al.
patent: 5262994 (1993-11-01), McClure
patent: 5265100 (1993-11-01), McClure et al.
patent: 5267210 (1993-11-01), McClure et al.

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