Semiconductor memory with an improved dummy cell arrangement and

Details Semiconductor memory with an improved dummy cell arrangement and Semiconductor memory with an improved dummy cell arrangement and

1987-04-10

1989-03-28

Hecker, Stuart N.

Static information storage and retrieval

Read only systems

Semiconductive

365210, 365200, 371 11, 371 38, G11C 1700, G06F 1100

Patent

active

048170526

ABSTRACT:
In a read only semiconductor memory, signal lines such as data lines are subjected to an undesired parasitic capacitance which restricts the signal changing rate along the lines. The parasitic capacitance which is driven by a memory cell will become increasingly higher as the memory capacity is increased. According to the present invention, a differential sense amplifier is used to amplify the data signals which are read out of the memory cell. At the same time, a dummy cell is used to generate a reference potential which is to be referred to by the differential sense amplifier. In particular, a dummy cell arrangement is provided wherein each dummy cell includes at least two series-connected semiconductor elements to provide a predetermined dummy cell conductance to establish a reference value. Another aspect of the invention lies in the use of column switches between a common data line and data lines of the memory arrays for coupling only one data line at a time through the column switch to the sense amplifier. In addition, a built-in error-correcting-code circuit is provided which operates in conjunction with a selecting circuit so that memory cells delivering a predetermined set of data are spaced apart from one another by at least predetermined distances to reduce the likelihood of errors from immediately adjacent memory cells.

REFERENCES:
patent: 3644902 (1972-02-01), Beausoleil
patent: 3920976 (1975-11-01), Christensen et al.
patent: 4031524 (1977-06-01), Heeren
patent: 4342102 (1982-07-01), Puar
patent: 4456995 (1984-06-01), Ryan

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