Semiconductor memory with alternately multiplexed row and column

Details Semiconductor memory with alternately multiplexed row and column Semiconductor memory with alternately multiplexed row and column

1990-08-16

1992-01-21

Clawson, Jr., Joseph E.

Static information storage and retrieval

Addressing

Multiplexing

36523008, 365233, G11C 804

Patent

active

050832964

ABSTRACT:
The semiconductor memory receives an external clock signal and has the memory cell array access operation controlled based on the clock signal. In the application of this semiconductor memory to a dynamic RAM, for example, a row address and column address are introduced in synchronism with the clock signal. The read, write and refresh operations are controlled based on the clock signal.

REFERENCES:
patent: 4831597 (1989-05-01), Fuse
patent: 4873663 (1989-10-01), Baranyai et al.
patent: 4912679 (1990-03-01), Shinoda et al.
patent: 4916670 (1990-04-01), Suzuki et al.
patent: 4985868 (1991-01-01), Nakano et al.

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