Static information storage and retrieval – Addressing – Multiplexing
Reissue Patent
1994-01-21
2004-01-06
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Addressing
Multiplexing
C365S230080, C365S233100
Reissue Patent
active
RE038379
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor memory, such as a dynamic RAM, for example.
Conventional semiconductor memories, such as dynamic RAMs, are based on the input multiplexing of the row address and column address, and they necessitate a row address strobe, column address strobe and several other timing signals including write control signals, as is well known in the art.
A computer system generally operates in synchronism with a constant system clock, and data to be read out or written into a storage unit is transferred also in synchronism with the system clock. Accordingly, for a storage unit based on the dynamic RAM, in which several timing signals are produced from the system clock, these timing signals need to be set to meet the prescribed timings even in the worst condition in consideration of the variability in the signal delay time, crosstalk noise, and the like. On this account, conventional semiconductor memories cannot fully exert their inherent performances.
SUMMARY OF THE INVENTION
An object of this invention is to provide a semiconductor memory, e.g., a dynamic RAM, which operates with its full performance.
The inventive address-multiplexed semiconductor memory is designed to receive a clock signal and a chip select signal from the outside and have its memory cell array access controlled based on the clock signal. Consequently, by supplying an external clock signal which meets the performance of the semiconductor memory, it can operate with its full performance.
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Hara Kouji
Kurihara Ryoichi
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Zarabian A.
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