Semiconductor memory with address input selection circuits

Details Semiconductor memory with address input selection circuits Semiconductor memory with address input selection circuits

2003-02-26

2004-10-26

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230020, C365S200000

Reexamination Certificate

active

06809988

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application is related to Japanese application JP 2002-054367 filed on Feb. 28, 2002, whose priority is claimed under 35 USC § 119, the disclosure of which is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory and, more specifically, to a semiconductor memory which, if having a defective memory cell therein, can be used as a memory having a smaller memory capacity than its original capacity without using an area in which the defective memory cell is present.
2. Description of the Related Art
An exemplary semiconductor memory of the aforesaid type is disclosed in Japanese Unexamined Patent Publication No. SHO 59 (1984)-40392. The construction of this semiconductor memory will be described with reference to FIG.
6
.
FIG. 6
illustrates an address data input section of the semiconductor memory. In
FIG. 6
, there are shown address input terminals (hereinafter referred to as “pins”)
11
0
to
11
n
for receiving plural address data bits A
0
to A
n
respectively supplied thereto, and address buffers
12
0
to
12
n
provided in one-to-one correspondence with the respective pins
11
0
to
11
n
for outputting address data pairs A
0
, A
0
(A
0
: the inverse of A
0
), A
1
, A
1
, . . . , and A
n
A
n
each having a complementary relationship on the basis of the address data bits A
0
to A
n
.
Enhancement-mode MOSFETs
13
0
to
13
n
are respectively inserted between the pins
11
0
to
11
n
and the corresponding address buffers
12
0
to
12
n
with drains and sources thereof connected to the pins
11
0
to
11
n
and the address buffers
12
0
to
12
n
. Further, enhancement-mode MOSFETs
14
0
to
14
n−1
are respectively inserted between the pins
11
0
to
11
n−1
and input terminals of the address buffers
12
1
to
12
n
at one-bit higher hierarchical levels with drains and sources thereof connected to the pins
11
0
to
11
n−1
and the address buffers
12
1
to
12
n
.
Gates of the MOSFETs
13
0
to
13
n
are connected via a common interconnection line
15
, while gates of the MOSFETs
14
0
to
14
n−1
are connected via a common interconnection line
16
.
An upper end of the interconnection line
15
as seen in
FIG. 6
is connected to a positive power supply voltage V
DD
via a depletion-mode MOSFET
17
. A gate of the MOSFET
17
is also connected to the power supply voltage V
DD
. A lower end of the interconnection line
15
as seen in
FIG. 6
is connected to a reference power supply voltage V
SS
via a depletion-mode MOSFET
18
. A gate of the MOSFET
18
is also connected to the power supply voltage V
SS
. The MOSFETs
17
,
18
are each properly dimensioned so that the interconnection line
15
is kept at a logic “1” level.
Where a logic circuit is employed which is operative on the basis of a 0-V signal defined as an L-level signal (low level signal) and a 5-V signal defined as an H-level signal (high level signal), for example, a logic “0” level and a logic “1” level herein mean the L-level signal and the H-level signal, respectively.
An upper end of the interconnection line
16
as seen in
FIG. 6
is connected to the reference power supply voltage V
SS
via a depletion-mode MOSFET
19
. A gate of the MOSFET
19
is also connected to the power supply voltage V
SS
. A lower end of the interconnection line
16
as seen in
FIG. 6
is connected to the power supply voltage V
DD
via a depletion-mode MOSFET
20
. A gate of the MOSFET
20
is also connected to the power supply voltage V
DD
. The MOSFETs
19
,
20
are each properly dimensioned so that the interconnection line
16
is kept at the logic “0” level.
FIGS.
7
(
a
) and
7
(
b
) illustrate address fixing circuits provided at address data output terminals of each of the address buffers
12
0
to
12
n
. The address fixing circuits are adapted to fix the output data A
i
, A
i
at given levels on the basis of control signals F
11
, F
12
irrespective of the address data applied to the output terminals. As shown in FIGS.
7
(
a
) and
7
(
b
), the address fixing circuits respectively include a pair of enhancement-mode MOSFETs
31
,
32
and a pair of enhancement-mode MOSFETs
33
,
34
.
The address data input section of the semiconductor memory is operative in the following manner. In a normal operation, all the MOSFETs
13
0
to
13
n
are in an ON state, and all the MOSFETs
14
0
to
14
n−1
are in an OFF state. Therefore, the address data bits A
0
to A
n
respectively supplied to the pins
11
0
to
11
n
are transferred to the input terminals of the corresponding address buffers
12
0
to
12
n
via the MOSFETs
13
0
to
13
n
the ON state. In this case, memory cells (not shown) of the semiconductor memory are all addressable on the basis of the address data bits A
0
to A
n
. That is, none of the memory cells of the semiconductor memory is defective.
FIG. 5
illustrates a memory cell array. It is assumed that a left half of the memory cell array is designated by an address data value A
n
=0 and a right half of the memory cell array is designated by an address data value A
n
=1. An explanation will be given to a case where a defective memory cell occurs in an area X in
FIG. 5
, i.e., in a memory area designated by the address data value A
n
=0.
In this case, the memory area (area X) designated by the address data value A
n
=0 is not used. To this end, the control signals F
11
to be applied to the address fixing circuits (FIGS.
7
(
a
) and
7
(
b
)) in the address buffer
12
n
are set at the “1” level. As a result, the address data value A
n
is set at A
n
=1 irrespective of the value of the address data bit supplied to the pin
11
n
, so that the memory area designated by the address data value A
n
=0 is not selected.
Therefore, even if the defective memory cell occurs in the area designated by the address data value A
n
=0 in the semiconductor memory, the semiconductor memory can be used as a memory having a memory capacity one half its original capacity without using the bin
11
n
at the highest hierarchical level.
Next, an explanation will be given to a case where defective memory cells occur in areas W
1
, W
3
in
FIG. 5
, i.e., memory areas designated by an address data value A
n−1
=0.
In this case, the memory areas (areas W
1
, W
3
) designated by the address data value A
n−1
=0 are not used. To this end, the control signals F
11
to be applied to the address fixing circuits (FIGS.
7
(
a
) and
7
(
b
)) in the address buffer
12
n−1
are set at the “1” level. As a result, the address data value A
n−1
is set at A
n−1
=1 irrespective of the value of the address data bit supplied to the pin
11
n−1
, so that the memory areas designated by the address data value A
n−1
=0 are not selected.
In this case, the MOSFETs
13
0
to
13
n−2
and
14
n−1
are set in the ON state, and the MOSFETs
14
0
to
14
n−2
,
13
n−1
and
13
n
are set in the OFF state for shifting a transfer line for the address data bit A
n−1
.
This setting is achieved by isolating the interconnection lines
15
and
16
from the MOSFETs
17
and
19
, respectively. More specifically, the interconnection lines
15
,
16
are composed of polycrystalline silicon or aluminum. The interconnection line
15
is fused off between gate junctions of the MOSFETs
13
n−2
and
13
n−1
and the interconnection line
16
is fused off between gate junctions of the MOSFETs
14
n−2
and
14
n−1
by laser radiation.
Thus, a part of the interconnection line
15
between the gate of the MOSFET
13
n−1
and the MOSFET
18
which has been kept at the logic “1” level is set at the logic “0” level, so that the MOSFETs
13
n−1
,
13
n
are turned off. Further, a part of the interconnection line
16
between the gate of the MOSFET
14
n−1
and the MOSFET
20
which has been kept at the logi

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