Semiconductor memory using multiple level storage structure

Details Semiconductor memory using multiple level storage structure Semiconductor memory using multiple level storage structure

1984-07-05

1987-11-24

Moffitt, James W.

Static information storage and retrieval

Analog storage systems

365184, G11C 2700

Patent

active

047093501

ABSTRACT:
In a semiconductor memory for reading and writing of stored charge in an X-Y address system by arranging a plurality of memory cells each including a capacitance element and one MOS-FET in matrix, this invention discloses a semiconductor memory using multiple level storage structure for read and write of at least more than two multi-level data stored in the capacitance elements, by applying a multi-level step voltage to the plate electrode of the capacitance or to the gate electrode of MOS-FET so as to write and read signal charge.

REFERENCES:
patent: 4300210 (1981-11-01), Chakravarti et al.
patent: 4459609 (1984-07-01), Fifield et al.

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