Semiconductor memory used for changing sequence of data

Details Semiconductor memory used for changing sequence of data Semiconductor memory used for changing sequence of data

1991-10-01

1993-10-12

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Combined random and sequential addressing

365239, 365240, 36523006, G11C 800, G11C 1300

Patent

active

052532135

ABSTRACT:
An SRAM adapted for changing the sequence of data. A counter 7 generates a sequentially increasing address signal. A write designation circuit 2a sequentially designates a memory cell row to be selected for writing in response to the address signal. Conversely, a read designation circuit 3a designates a memory cell row in response to the address signal in a sequence determined by a predetermined rule. The generation of an address signal, which changes in a complicated manner and is required for changing the sequence of data, is not required, so that the amount of the operation process by the CPU is decreased.

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"Principles of CMOS VLSI Design, A Systems Perspective", Weste et al., Addison-Wesley Publishing Company pp. 348-349.

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