Semiconductor memory unit in which power consumption can be...

Details Semiconductor memory unit in which power consumption can be... Semiconductor memory unit in which power consumption can be...

2001-11-13

2003-03-18

Lam, David (Department: 2818)

Static information storage and retrieval

Powering

Conservation of power

C365S226000, C365S233100

Reexamination Certificate

active

06535449

ABSTRACT:

BACKGROUND OF THE INVENTION
1. (Field of the Invention)
The present invention relates to a semiconductor memory unit in which power consumption can be restricted in accordance with an input voltage inputted from a plurality of source voltages.
2. (Description of the Prior Art)
A semiconductor memory unit which is operable at a plurality of source voltages such as 5V and 3.3V is known. Meanwhile, a plurality of upper current consumption thresholds are, respectively, provided for the source voltages. Usually, as the source voltages rise higher, the upper current consumption thresholds are also set higher. This is because low-voltage operation is employed for the purpose of lowering power consumption.
In order to operate the semiconductor memory unit at higher speed, it is considered pertinent to employ a method in which operating frequency of an internal control circuit is raised, a method in which the number of nonvolatile memories accessible at a time are increased for their parallel processing, etc.
FIG. 5
shows a configuration of a conventional semiconductor memory unit
10
which is operable at a plurality of source voltages. The conventional semiconductor memory unit
10
includes a host interface circuit
11
for effecting data input-output from and to a host system, a central processing unit (CPU)
12
for controlling the semiconductor memory unit
10
, an error check and correct (ECC) circuit
13
for upgrading reliability of the data at the time of transfer of the data, a plurality of buffers
14
utilized for the data input-output, a control circuit
15
for producing a waveform necessary for the data transfer, a plurality of nonvolatile memories
16
for storing the data and a clock generator
17
for actuating internal circuits of the semiconductor memory unit
10
.
In the case of data write, the data is delivered from the host system to the buffer
14
via the host interface circuit
11
. Thereafter, the data in the buffer
14
is decoded by the ECC circuit
13
and then, is stored in the nonvolatile memory
16
. The CPU
12
transfers the data by using the control circuit
15
. Data transfer time is determined by an operating frequency of clocks supplied from the clock generator
17
to the CPU
12
, the control circuit
15
and the ECC circuit
13
. In case the operating frequency of the clocks is high, processing is performed at high speed but current consumption increases.
In the conventional semiconductor memory unit
10
, data transfer rate can be raised by using a plurality of the buffers
14
alternately.
FIG. 6
schematically shows processing sequences of data write in the conventional semiconductor memory unit
10
. By allocating write data to a plurality of the nonvolatile memories
16
, write is performed simultaneously and thus, processing time can be shortened. At this time, as the number of the nonvolatile memories
16
operated at a time increases further, operating current rises higher.
In the conventional semiconductor memory unit
10
shown in
FIGS. 5 and 6
, such a disadvantage is incurred that since a function of detecting an input voltage inputted to the semiconductor memory unit
10
from a plurality of the source voltages is not provided, a minimum of a plurality of maximum permissible current consumption values corresponding to a plurality of the source voltages, respectively is required to be set at an upper current consumption threshold.
SUMMARY OF THE INVENTION
Accordingly, an essential object of the present invention is to provide, with a view to eliminating the above mentioned drawback of prior art, a semiconductor memory unit which operates at an optimum performance corresponding to an input voltage inputted from a plurality of source voltages.
In order to accomplish this object of the present invention, a semiconductor memory unit which includes a plurality of nonvolatile memories for storing data and is operable at a plurality of source voltages, according to the present invention comprises: a voltage detector for detecting an input voltage inputted to the semiconductor memory unit from the source voltages; and a central processing unit (CPU) which sets a maximum permissible current consumption value of the semiconductor memory unit on the basis of the input voltage and controls the number of the nonvolatile memories operated at a time such that a current consumption value of the semiconductor memory unit does not exceed the maximum permissible current consumption value.


REFERENCES:
patent: 5818781 (1998-10-01), Estakhri et al.
patent: 5-282067 (1993-10-01), None
patent: 7-287699 (1995-10-01), None
patent: 2000-172383 (2000-06-01), None

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