Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Patent
1995-02-28
1997-05-20
Lane, Jack A.
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
36523005, G11C 700
Patent
active
056318693
ABSTRACT:
A memory unit includes a plurality of read bit lines, a plurality of read word lines, a plurality of write bit lines, and a plurality of write word lines. An array of memory cells are connected to the read bit lines, the read word lines, the write bit lines, and the write word lines. Each of the memory cells includes at least two input sections, at least two output sections, and a memory element. The output sections are connected to at least two of the read word lines, respectively, and output data from the memory element to one of the read bit lines in response to signals on the read word lines. The input sections are connected to at least two of the write word lines, respectively, and output data from one of the write bit lines into the memory element in response to signals on the write word lines. A plurality of decoders connected to the read word lines decode a read address signal into output signals, respectively, which are fed to the read word lines. A plurality of decoders connected to the write word lines decode a write address signal into output signals, respectively, which are fed to the write word lines.
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Sheldon S. Chang "Multiple-Read Single-Write Memory and Applications" IEEE Transactions on Computers, vol. C.29, No. 8, Aug., 1980.
Kawada Tomoharu
Ninomiya Kazuki
Lane Jack A.
Matsushita Electric Industrial Co Ltd.
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