Semiconductor memory that enables high speed operation

Details Semiconductor memory that enables high speed operation Semiconductor memory that enables high speed operation

2001-05-24

2002-05-21

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S200000, C365S230030

Reexamination Certificate

active

06392956

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory. More particularly, the present invention relates to a semiconductor memory suitable for DRAM that enables a high-speed operation.
2. Description of the Related Art
FIG. 1
is a block diagram showing the configuration of a conventional technique. A semiconductor memory divided into regions of predetermined units referred to as blocks. Each block is selected by using a block selection signal BS that is an output from a block selection circuit
1
.
This semiconductor memory is provided with a memory cell section
5
, a redundancy memory cell section
6
, a word reset circuit
27
, pre-charge circuits
31
and sense amplifiers
32
.
The memory cell section
5
makes a predetermined memory cell
11
active based on an main word decoder address signal MWDA and a block selection signal BS. The redundancy memory cell section
6
makes a predetermined redundancy memory cell
21
active based on a redundancy word selection signal RWS and a block selection signal BS. The word reset circuit
27
generates a word reset signal WLR from a block selection signal, and also controls a selected word driver circuit
14
and a redundancy word driver circuit
24
. The pre-charge circuit
31
charges bit lines to (½) VCC. The sense amplifier
32
amplifies a cell data read out to the bit lines.
The memory cell section
5
comprises memory cells
11
, a word decoder
13
, word driver circuits
14
and a main word decoder
15
.
The memory cells
11
are the memory cells for storing data. The word decoder
13
outputs word decode signals (only two signals RA, RA+1 are shown as the representation) based on an address signal from an address buffer
4
and a block selection signal BS. The word driver circuit
14
drives word lines (only two lines WL, WL+1 are shown as the representation) selected by the word decode signals (RA, RA+1) in order to make the predetermined memory cells
11
active. There is a plurality of word driver circuits
14
in the memory cell section
5
. The main word decoder
15
generates a main word signal which changes the potential level of the main word lines (WLP to WLP+n) in order to select a predetermined word driver circuit
14
from the plurality of word driver circuits
14
.
The memory cell section
6
comprises redundancy memory cells
21
, a redundancy word decoder
23
, a redundancy word driver circuit
24
and a redundancy main word decoder
25
. The redundancy memory cells
21
are the memory cells for storing data. The redundancy word decoder
23
outputs redundancy word decode signals (only two signals RRA, RRA+1 are shown as the representation) based on a block selection signal BS. The redundancy word driver circuit
24
drives redundancy word lines (only two lines RWL, RWL+1 are shown as the representation) selected by the redundancy word decode signals (RRA, RRA+1) in order to make the predetermined redundancy memory cell
21
active. The redundancy main word decoder
25
generates a redundancy main word signal, which changes the potential level of the redundancy main word line RWLP in order to select a redundancy word driver circuit
24
.
The memory cell
11
and the redundancy memory cell
21
comprise n-MOSFETs and capacitance elements, respectively as shown in FIG.
4
. The standard potential is (½) VCC.
FIG. 2
shows the conventional reset circuit. The word reset circuit
27
is provided with a delay circuit
27
a
, a NAND
27
b
, inverter
27
c
and inverter
27
d
.
The word driver circuit
14
is controlled based on a voltage of the main word line WLP. It comprises a transistors T
1
to T
8
.
The transistor T
1
has a source connected to the word decoder
13
, a gate connected to the drain of the transistor T
2
, and a drain connected to one of word lines WL. The transistor T
1
makes one of word lines WL active by using the word decode signal RA. The transistor T
2
has a source connected to the main word decoder
15
, a gate connected to a high potential level power supply VCC, and a drain connected to the gate of the transistor T
1
. The transistor T
3
has a source connected to a low potential level power supply GND, a gate connected to a pull-down signal line
14
L for the pull-down signal
14
a
, and a drain connected to the word line WL. The transistor T
102
makes the active word line WL inactive by using a pull-down signal
14
a
. The transistor T
4
has a source connected to a pull-down signal line
14
L for the pull-down signal
14
a
, a gate connected to an output of the word reset circuit
27
, and a drain connected to a high potential level power supply VCC. The transistor T
5
has a source connected to a low potential level power supply GND, a gate connected to the main word line WLP, and a drain connected to the pull-down signal line
14
L.
Since the transistors T
6
to T
8
correspond to the transistors T
1
to T
3
respectively, the explanation for the transistors T
6
to T
8
are omitted.
The redundancy word driver circuit
24
is configured similarly to that of the word driver circuit
14
. The redundancy word driver circuit
24
is designed so as to be selected by using the word reset signal WLR of the word reset circuit
27
.
In the conventional operation of activating a word line WL, the operation timing having the above-mentioned configuration will be described below with reference to FIG.
5
.
In the conventional circuit, the redundancy main word line RWLP is not operated in a case of a selection of the memory cell
11
. It is operated only when the redundancy cell
21
is selected. Thus, the input of the word reset circuit
27
uses the block selection signal BS.
It is necessary to prevent an penetration current (excessive current) from flowing through the transistors T
4
and T
5
, when the transistors T
4
and T
5
of
FIG. 2
are turned on at the same time. It occurs at the timing that the word reset signal WLR is activated at the same timing of pulling up the potential level of main word line WLP.
An general decoder circuit is constituted by several stages of logical gates, as illustrated by an example shown in FIG.
3
. Typically, as the number of addresses is increased, the number of gate stages is increased, and a gate delay is also added.
The word reset circuit
27
has a delay circuit, correspondingly to the configuration of the main word decoder circuit. The delay circuit is adjusted so that the transistors T
4
and T
5
of
FIG. 2
are not turned on at the same time.
As for the operational timing to select a predetermined word driver circuit
14
from the plurality of word driver circuits
14
in
FIG. 5
, firstly, the block selection signal BS becomes the high potential level. At a time t
1
, the transistor T
4
is on, and the transistor T
5
is off. After the time t
1
, the word reset signal WLR becomes the low potential level. At a time t
3
, both the transistors T
4
and T
5
are off. After the time t
3
, the main word line WLP becomes the high potential level. At and after a time t
5
, the transistor T
4
is off, and the transistor T
5
is on. After the time t
5
, a contact R becomes the low potential level.
Also, to deselect a predetermined word driver circuit
14
, firstly, the block selection signal BS becomes the low potential level. Then, the main word line WLP becomes the low potential level. At a time t
4
, both the transistors T
4
and T
5
are off. After the time t
4
, the word reset signal WLR becomes the high potential level. At the time t
6
, the transistor T
4
is on, and the transistor T
5
is off. After a time t
6
, the contact R becomes the high potential level.
By considering the yield of the memory cell array, especially by considering the using redundancy memory cells
21
, this is designed so as to give a margin to the time t
4
by using the delay circuit
27
a.
In this way, the above-mentioned circuits can attain the expected operation by using the delay circuit
27
a
. However, the rising timing of the word reset signal WLR is delayed

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