Semiconductor memory test system

Details Semiconductor memory test system Semiconductor memory test system

1996-06-21

1998-05-26

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

057578150

ABSTRACT:
A semiconductor test system facilitates failure analysis of memory devices by being able to switch one situation where expected data used for an address fail memory is the same as data showing charge/discharge states in the memory cells of a memory device under test and another situation where the expected data is the same as data showing the expected output data of the device under test. For doing this, the semiconductor test system includes a prohibit means 7 for prohibiting the output of the an area inversion memory 22 from transferring to later stages, and an exclusive OR gate 6 which receives an output of the prohibit means 7 at one input and an output of an exclusive OR gate 23 at another input. The exclusive OR gate 6 supplies a resulted output to an address fail memory 5.

REFERENCES:
patent: 5579251 (1996-11-01), Sato
patent: 5604756 (1997-02-01), Kawara

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