Semiconductor memory test pattern generating apparatus

Details Semiconductor memory test pattern generating apparatus Semiconductor memory test pattern generating apparatus

1980-10-08

1983-08-30

Malzahn, David H.

Excavating

371 27, G06F 1100

Patent

active

044020813

ABSTRACT:
A semiconductor memory test pattern generating apparatus in which an instruction memory is read out, assigning an address by a program counter, and instructions thus read out are decoded and executed to generate a test pattern. A start address and a stop address and index data indicating the number of times of executing an area defined by the start and stop addresses are stored in a loop memory. During the operation of the program counter the start and stop addresses and the index data are read out from the loop memory and loaded in a register group. When the program counter coincides with the loaded stop address, the setting of the program counter to the loaded start address is executed by the number of times indicated by the loaded index data, and in the last execution the next address of the loop memory is read out.

REFERENCES:
patent: 4263669 (1981-04-01), Starger et al.
patent: 4293950 (1981-10-01), Shimizu et al.
patent: 4300234 (1981-11-01), Maruyama et al.
Geffken "Memory Tester Pattern Generator" IBM Tech. Disclosure Bulletin vol. 20, No. 2 Jul. 1977, pp 535-536.

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