Semiconductor memory test equipment

Details Semiconductor memory test equipment Semiconductor memory test equipment

1980-11-10

1983-01-18

Atkinson, Charles E.

Excavating

324 73R, 371 25, 371 27, G01R 3128

Patent

active

043695116

ABSTRACT:
A semiconductor memory test equipment which reads out a memory under test by an address from a pattern generator and compares the read-out data with an expected value by a comparator, and in which a block mask memory is read out by a portion of the address and the comparing operation of the comparator is inhibited by block mask data read out from the block mask memory. Pattern data for a pattern memory, which is read out by the abovesaid address to store data to be supplied to the comparator, are transferred as parallel data from a central processor and written in the pattern memory after conversion to serial data, and serial data read out from a defective address memory are inputted to the central processor after conversion to parallel data.

REFERENCES:
patent: 3311890 (1967-03-01), Waaben
patent: 3631229 (1971-12-01), Bens
patent: 3751649 (1973-08-01), Hart, Jr.
patent: 3962687 (1976-06-01), Suzumura et al.
patent: 4293950 (1981-10-01), Shimizu et al.
J. McLeod, Pattern Processor Packs Hardware, Software Generators, Electronic Design, vol. 28, No. 23, Nov. 8, 1980, pp. 36, 37.

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