Semiconductor memory system with bank switching control

Details Semiconductor memory system with bank switching control Semiconductor memory system with bank switching control

1998-07-30

2000-01-04

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

36518905, G11C 800

Patent

active

060117451

ABSTRACT:
When a particular bank is selected the output from the data AMP of that bank is inputted and latched, and the data corresponding to the output of the data AMP is transmitted to the common data transmission line RWBUS. When the particular bank is not selected, the data on the common data transmission line RWBUS is latched to hold the final data of the previous bank during the cycle time tCK period even when the bank is switched over during the read operation, and the data on the common data transmission line RWBU can be latched, thereby enabling increased speed of the read action.

REFERENCES:
patent: 5764590 (1998-06-01), Iwamoto et al.
patent: 5784705 (1998-07-01), Leung

Affiliated with

Also associated with

Rating

Semiconductor memory system with bank switching control does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory system with bank switching control, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory system with bank switching control will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1077822