Semiconductor memory structure with stress regions

Details Semiconductor memory structure with stress regions Semiconductor memory structure with stress regions

2011-08-30

2011-08-30

Le, Thao P. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

With current flow along specified crystal axis

C257SE29004

Reexamination Certificate

active

08008692

ABSTRACT:
A semiconductor memory structure with stress regions includes a substrate defining a first and a second device zone; a first and a second stress region formed in each of the first and second device zone to yield stress different in level; a barrier plug separating the two device zones from each other; and a plurality of oxide spacers being located between the first stress regions and the barrier plug while in direct contact with the first stress regions. Due to the stress yielded at the stress regions, increased carrier mobility and accordingly, increased reading current can be obtained, and only a relatively lower reading voltage is needed to obtain an initially required reading current. As a result, the probability of stress-induced leakage current is reduced to enhance the data retention ability.

REFERENCES:
patent: 2008/0230845 (2008-09-01), Okonogi et al.
patent: 2009/0032844 (2009-02-01), Ogura et al.
patent: 2009/0079008 (2009-03-01), Nandakumar et al.
patent: 2009/0294986 (2009-12-01), Yan et al.

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