Semiconductor memory, semiconductor integrated circuit and...

Details Semiconductor memory, semiconductor integrated circuit and... Semiconductor memory, semiconductor integrated circuit and...

2001-09-26

2003-12-09

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S063000, C365S230060

Reexamination Certificate

active

06661731

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims benefit of priority under 35 U.S.C. §119 to Japanese Patent Application No. 2000-295,219 filed on Sep. 27, 2000, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This application relates to a semiconductor memory, a semiconductor integrated circuit and a semiconductor mounted device, and more particularly relates to a semiconductor memory which is accessed by a plurality of interfaces, a semiconductor integrated circuit including such a semiconductor memory, and a semiconductor mounted device in which the semiconductor memory is mounted on a system board.
2. Description of the Related Art
A system LSI such as a micro-processor and a graphic LSI is provided with a built-in memory such as a cache memory in order to improve system characteristic thereof. Such memories store a part of data which are stored in a higher order memory connected to a system bus, thereby reducing the number of accesses to data via the system bus, and enabling high speed access to the data.
Referring to
FIG. 1
of the accompanying drawings, a built-in memory
103
included in a system LSI
100
is required to have a system bus interface for transmitting and receiving data to and from a higher order memory (not shown), and a CPU interface for transmitting and receiving the data to and from a central processing unit (CPU). The built-in memory
103
has only one port for a system bus
101
S and a CPU bus
101
C, so that a multiplexer
102
is used for selectively establishing a connection between the system bus interface and the system bus
101
S or a connection between the CPU interface and the CPU bus
101
C. The multiplexer
102
is activated in response to a selective control command from an arbiter circuit
104
.
The data in the built-in memory
103
cannot be accessed by the system bus interface and the CPU bus interface at the same time. If the data are continuously and preferentially accessed by the CPU bus
101
C under control of the arbiter circuit
104
, the system bus
101
S cannot access the data. As a result, the system characteristics of the system LSI
100
will be reduced.
In order to overcome the reduced system characteristics caused by data access collision, the built-in memory
103
is preferably provided with a plurality of banks.
Referring to
FIG. 2
, a built-in memory
103
includes two memory banks
103
B
0
and
103
B
1
, each of which has a half of the whole storage capacity. System interfaces of the memory banks
103
B
0
and
103
B
1
are respectively connected to a system bus
101
S via a multiplexer
102
A, which selects the system interface of either the memory bank
103
B
0
or
103
B
1
in response to a bank address signal from a system bus address. On the other hand, CPU interfaces of the memory banks
103
B
0
and
103
B
1
are connected to a CPU bus
101
C via a multiplexer
102
B, which selects the CPU interface of either the memory bank
103
B
0
or
103
B
1
.
The data in the built-in memory
103
shown in
FIG. 2
can be accessed by both of the foregoing interfaces so long as different bank address signal are used. Further, even if the data are continuously accessed by one of the foregoing interfaces, they can be also accessed by the other interface with a probability of ½. Therefore, the data are accessible from both of the foregoing interfaces without a long waiting time, which is effective in improving the system characteristics of the system LSI
100
.
However, the built-in memory
103
requires the memory banks
103
B
0
and
103
B
1
as shown in
FIG. 2
, which means that a bit width of a memory cell array of the built-in memory
103
is simply doubled. Especially, the system LSI
100
processes signals using a number of bits in order to accelerate a processing operation, so that the built-in memory
103
tends to require more bits. Therefore, it becomes difficult to constitute memory cell arrays in the built-in memory
103
. Further, an aspect ratio (i.e. a ratio between a column size and a row size) is increased, which inevitably enlarges the built-in memory
103
. The larger the built-in memory
103
, the longer the access time of the built-in memory
103
.
In the built-in memory
103
having the two-bank structure, the same data bits are present in the memory banks
103
B
0
and
103
B
1
. As shown in
FIG. 3
, a data bus wiring
105
is necessary to connect an interface between the memory banks
103
B
0
and
103
B
1
. The data bus wiring
105
has to be as long as the columns of the memory banks
103
B
0
and
103
B
1
. As a result, the system LSI
100
should be enlarged in order to house the data bus wiring
105
. The access time is inevitably increased due to a wiring delay of the data bus wiring
105
.
BRIEF SUMMARY OF THE INVENTION
According to a first aspect of the invention, there is provided a semiconductor memory comprising: a plurality of sub-memory cell arrays each of which is constituted by a plurality of memory cells arranged in a first direction; a memory cell array constituted by the sub-memory cell arrays arranged in the first direction and a second direction traversing the first direction; a plurality of local bit lines connected in parallel to a plurality of the memory cells in the sub-memory arrays; a plurality of word lines connected to the memory cells in the sub-memory arrays; a plurality of global bit lines connected in parallel to the local bit lines in the sub-memory cell arrays arranged in the first direction via switching circuits, and arranged in the second direction; a plurality of read/write circuits connected to the global bit lines, and reading and writing information from and into the memory cells; a selecting circuit selecting a first read/write circuits on the basis of a first address signal from a first bus and selecting a second read/write circuits on the basis of a second address signal from a second bus; a sub-memory cell array selecting circuit connected to the switching circuits, decoding the first and second address signals, and selecting a first sub-memory cell array on a first global bit line connected to the first read/write circuit, and a second sub-memory cell array on a second global bit line connected to the second read/write circuits; and an address decoding circuit decoding the first and second address signals, and activating a first word line connected to a memory cell of the first sub-memory cell array and a second word line connected to another memory cell of the second sub-memory cell array.
In accordance with a second aspect of the invention, there is provided a semiconductor memory comprising: a plurality of sub-memory cell arrays each of which is constituted by a plurality of memory cells arranged in a first direction; a memory cell array constituted by the sub-memory cell arrays arranged in the first direction and a second direction traversing the first direction; a plurality of local bit lines connected in parallel to a plurality of the memory cells in the sub-memory arrays; a plurality of word lines connected to the memory cells in the sub-memory arrays; a plurality of global bit lines extending along the local bit lines in the sub-memory cell arrays arranged in the first direction, and arranged in the second direction; a plurality of switching circuits provided to the global bit lines, and connected to the local bit line of a first global bit line or a second global bit line which is adjacent in the second direction; a plurality of read/write circuits connected to the global bit lines, and reading and writing information from and into the memory cells; a sub-memory cell array selecting circuit connected to the switching circuits, decoding the first and second address signals, and selecting a first sub-memory cell arrays on the first global bit lines connected to a first read/write circuit, and a second sub-memory cell array on the second global bit line connected to a second read/write circuits, or the sub-memory cell array selecting circuit selecting a

Affiliated with

Also associated with

Rating

Semiconductor memory, semiconductor integrated circuit and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory, semiconductor integrated circuit and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory, semiconductor integrated circuit and... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3108700