Semiconductor memory operating with low supply voltage

Details Semiconductor memory operating with low supply voltage Semiconductor memory operating with low supply voltage

1990-11-29

1993-11-23

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 3072968, 3072965, H03K 1900

Patent

active

052647439

ABSTRACT:
The present invention is intended to operate a semiconductor device at high speed with low voltage. A circuit configuration is used in which the transfer impedance between a common I/O line and a data line is changed depending on whether information is to be read or written. A current/voltage converter is provided which includes a MISFET different in conduction type to a select MISFET. Thus, the speed of reading information is increased. An intermediate voltage generator having high driving capability is provided. Thus, the circuit has sufficient driving capability for an LSI having large load capacitance. A voltage converter is provided which converts a data line supply voltage or word line supply voltage to a higher voltage. Therefore, stabilized signal transmission is ensured.

REFERENCES:
patent: 4988888 (1991-01-01), Hirose et al.
patent: 5055713 (1991-10-01), Watanabe et al.
patent: 5075577 (1991-12-01), Okitaka
patent: 5083043 (1992-01-01), Yoshida
patent: 5140194 (1992-08-01), Okitaka
Tohru Furuyama, et al., "An Experimental 4-Mbit CMOS DRAM", IEEE Journal of Solid-State Circuits, vol. SC-21, No. 4, Oct. 1986, pp. 605-610.
Takashi Ohsawa, et al., "A 60-ns 4-Mbit CMOS DRAM with Built-In Self-Test Function", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987, pp. 663-667.
Katsutaka Kimura, et al., "Power Reduction Techniques in Megabit DRAM's", IEEE Journal of Solid-State Circuits, vol. SC-21, No. 3, Jun. 1986, pp. 381-389.
Syuso Fujii, et al., "A 50-u A Standby 1M.times.1/256K.times.4 CMOS DRAM with High-Speed Sense Amplifier", IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5, Oct. 1986, pp. 643-647.
Masakazu Aoki, et al., "A 60-ns 16-Mbit CMOS DRAM with Transposed Data-Line Structure", IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, pp. 1113-1119.
Kazumasa Yanagisawa, et al., "A 23ns 1Mbit BiCMOS DRAM", ESSCIRC Digest of Technical Papers, Sep. 1989, pp. 184-187.

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